Patents Examined by Hoa B. Trinh
  • Semiconductor device having well with peak impurity concentrations and method for fabricating the same
    Patent number: 7592241
    Abstract: The semiconductor device comprises a well 58 formed in a semiconductor substrate 10 and having a channel region; a gate electrode 34n formed over the channel region with an insulating film 32 interposed therebetween; source/drain regions 60 formed in the well 58 on both sides of the gate electrode 34n, sandwiching the channel region; and a pocket region 40 formed between the source/drain region and the channel region. The well 58 has a first peak of an impurity concentration at a depth deeper than the pocket region 40 and shallower than the bottom of the source/drain regions 60, and a second peak of the impurity concentration at a depth near the bottom of the source/drain regions 60.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 22, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Yoshihiro Takao
  • Semiconductor device
    Patent number: 7576419
    Abstract: A semiconductor device has an IC chip main body including a power transistor and a substrate of BGA type including an insulating substrate. A plurality of external electrodes are formed on a plurality of through holes formed in the insulating substrate so as to individually penetrate from one surface to the other surface and protrude to the other surface. Further, the external electrodes are arranged in a grid pattern. Power pads among IC pads of the IC chip main body are bonded to substrate pads connected to outermost peripheral external electrodes among the external electrodes of the substrate, such that the lengths of the wires become shorter.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: August 18, 2009
    Assignee: Rohm Co., Ltd.
    Inventor: Masashi Horimoto
  • Packed system of semiconductor chips having a semiconductor interposer
    Patent number: 7573139
    Abstract: A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: August 11, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Mark A. Gerber, Kurt P. Wachtler, Abram M. Castro
  • Wiring board and ceramic chip to be embedded
    Patent number: 7557440
    Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: July 7, 2009
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Akifumi Tosa
  • Glass substrate and capacitance-type pressure sensor using the same
    Patent number: 7535096
    Abstract: A glass substrate has a pair of main surfaces opposite to each other. Two island-shaped portions made of silicon are buried in the glass substrate. The two island-shaped portions are exposed from the two main surfaces of the glass substrate, respectively. An electrode is formed on one main surface of the glass substrate so as to be electrically connected to one exposed portion of one island-shaped portion, and another electrode is formed thereon so as to be electrically connected to one exposed portion of the other island-shaped portion. Still another electrode is formed on the other main surface of the glass substrate so as to be electrically connected to the other exposed portion of the one island-shaped portion. A silicon substrate having a pressure sensing diaphragm is bonded to the other main surface of the glass substrate.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 19, 2009
    Assignee: Alps Electric Co., Ltd.
    Inventors: Manabu Tamura, Takashi Hatanai, Kazuhiro Soejima, Koichi Takahashi, Munemitsu Abe, Shinji Murata
  • Semiconductor device and method of manufacturing same
    Patent number: 7482182
    Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: January 27, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideaki Kuwabara
  • Underfill and mold compounds including siloxane-based aromatic diamines
    Patent number: 7479449
    Abstract: A method including introducing a composition including a siloxane-based aromatic diamine in a flowable state between a first substrate including a first set of contact points and a second substrate including a second set of contact points coupled to the first substrate through interconnections between a portion of the first set of contact points a portion of the second set of contact points; and curing the composition.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventor: Saikumar Jayaraman
  • Side-view type light emitting device
    Patent number: 7479665
    Abstract: A side-view type light emitting device capable of effectively releasing heat generated on the surface of the substrate is provided. The side-view type light emitting device 1 comprising a substrate 1-1, a positive surface electrode 1-2, a negative surface electrode 1-3, a light emitting element 1-4, a sealing member 1-5 sealing the light emitting element 1-4, a positive rear surface electrode 1-6, a negative rear surface electrode 1-7, and a short-cut preventing member 1-8. The positive surface electrode 1-2 and the positive rear surface electrode 1-6 are electrically connected via a first through hole 1-9 and the negative surface electrode 1-3 and the negative rear surface electrode 1-7 are electrically connected via a second through hole 1-10.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: January 20, 2009
    Assignee: Nichia Corporation
    Inventors: Kenji Takine, Ryohei Yamashita
  • Integrated chip carrier with compliant interconnect
    Patent number: 7473577
    Abstract: An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top side connected to the bottom side of the chip by solder bumps. The carrier further includes a second CTE that approximately matches the first CTE, and a plurality of through vias from the bottom side of the carrier to the top side of the carrier layer. Each through via comprising a collar exposed at the top surface of the carrier, a pad exposed at the bottom surface of the carrier, and a post disposed between the collar and the pad. The post extends thorough a volume of space.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventor: Timothy J. Chainer
  • LED packaging
    Patent number: 7470935
    Abstract: An LED packaging construction has a chip embedded on a recessed carrier on substrate; conduction circuits with different electrodes being disposed to the peripheral of the carrier; electrode layer of chip being connected to conduction circuits with golden plated wire; fluorescent powder being filled in the carrier before mounting the colloid on the powder layer; coverage of colloid extending to substrate to complete LED packaging; larger binding range between colloid and substrate yielding better strength and increased light-emitting angle of the chip through the colloid.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: December 30, 2008
    Assignee: Taiwan Oasis Technology Co., Ltd.
    Inventors: Ming-Shun Lee, Ping-Ru Sung
  • LED package and fabricating method thereof
    Patent number: 7453093
    Abstract: The invention provides an LED package capable of effectively releasing heat emitted from an LED chip out of the package and a fabrication method thereof. For this purpose, at least one groove is formed on an underside surface of the substrate to package the LED chip and the groove is filled with carbon nanotube material. In the LED package, a substrate having at least one groove on the underside surface is prepared. A plurality of electrodes are formed on a top surface of the substrate. Also, at least the one LED chip is mounted over the substrate to have both terminals electrically connected to the upper electrodes. In addition, carbon nanotube filler is filled in the groove of the substrate.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: November 18, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Suk Kim, Young Soo Oh, Hyoung Ho Kim, Taek Jung Lee, Seog Moon Choi
  • Epitaxial wafer for semiconductor light-emitting devices, and semiconductor light-emitting device
    Patent number: 7449720
    Abstract: An epitaxial wafer for semiconductor light-emitting devices has an n-type substrate, on which are sequentially formed an n-type cladding layer, an active layer, a p-type cladding layer having Mg as a p-type dopant, and a p-type cap layer. The p-type cap layer has at least two Mg-doped and Zn-doped layers that are formed sequentially from the substrate side.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: November 11, 2008
    Assignee: Hitachi Cable, Ltd.
    Inventors: Ryoji Suzuki, Akio Ohishi
  • Method of driving a light emitting device
    Patent number: 7445946
    Abstract: The present invention is characterized in that a transistor with its L/W set to 10 or larger is employed, and that |VDS| of the transistor is set equal to or larger than 1 V and equal to or less than |VGS?Vth|. The transistor is used as a resistor so that the resistance of a light emitting element can be held by the transistor. This slows down an increase in internal resistance of the light emitting element and the resultant current value reduction. Accordingly, a change with time in light emission luminance is reduced and the reliability is improved.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: November 4, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsuaki Osame, Jun Koyama
  • Active matrix substrate and repairing method thereof
    Patent number: 7439589
    Abstract: An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged in a matrix in the active region. The driving lines electrically connected to the pixels are disposed in the active region and the peripheral region. The ESD protection circuit and the floating line are disposed in the peripheral region of the substrate. The ESD protection circuit is electrically connected to the driving lines. The ESD protection circuit includes an outer short ring (OSR) and an inner short ring (ISR) disposed between the pixel units and the OSR. The floating line is located beside the outer driving line.
    Type: Grant
    Filed: February 26, 2006
    Date of Patent: October 21, 2008
    Assignee: Au Optronics Corporation
    Inventor: Han-Chung Lai
  • LED module
    Patent number: 7439549
    Abstract: An LED module has a carrier, which contains a semiconductor layer and has a planar main area, on which LED semiconductor bodies are applied. Use is preferably made of LED semiconductor bodies which emit light of differing central wavelengths during operation, so that the LED module is suitable for generating mixed-color light, and in particular for generating white light.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: October 21, 2008
    Assignee: Osram GmbH
    Inventors: Werner Marchl, Werner Späth, Günter Waitl
  • Semiconductor device having a trench surrounding each of plural unit cells
    Patent number: 7429768
    Abstract: A semiconductor device comprises a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET). The unit cell includes a first source region formed in a first base region, a second source region formed in the first base region and separated from the first source region, and a second base region formed in the first base region and disposed between the first and second source regions. The semiconductor device further comprises a trench gate formed in a vicinity of each of the plurality of unit cells. The second base region of an unit cell is separated from the second base region of an adjacent unit cell, and the first or second source region of an unit cell is separated from the first or second source region of an adjacent unit cell.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 30, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Kenya Kobayashi
  • Double gate MOSFET device
    Patent number: 7423321
    Abstract: A method of fabricating a double gate MOSFET device is provided. The present invention overetches a silicon layer overlying a buried oxide layer using a hard mask of cap oxide on the silicon layer as an etching mask. As a result, source, drain and channel regions are formed extending from the buried oxide layer, and a pair of recesses are formed under the channel regions in the buried oxide layer. The channel is a fin structure with a top surface and two opposing parallelly sidewalls. The bottom recess is formed under each opposing sidewall of the fin structure. A conductive gate layer is formed straddling the fin structures. The topography of the conductive gate layer significantly deviates from the conventional plainer profile due to the bottom recess structures under the channel regions, and a more uniformly distributed doped conductive gate layer can be obtained.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: September 9, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Shiang Liao, Wei-Tsun Shiau
  • Molded stiffener for thin substrates
    Patent number: 7423331
    Abstract: A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate by a molding technique such as transfer molding, injection molding, and spray molding, or using an encapsulating material. One or more dies, chips, or other semiconductor or microelectronic devices can be disposed on the substrate to form a die assembly. The stiffener can be molded to a substrate comprising one or more dies, over which an encapsulating material can be applied to produce a semiconductor die package.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: September 9, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Chad A Cobbley, Cary J Baerlocher
  • Integrated circuit device package having a support coating for improved reliability during temperature cycling
    Patent number: 7423337
    Abstract: An apparatus and method for increasing integrated circuit device package reliability is disclosed. According to one embodiment of the present invention, a support coating is added to a wafer after solder bumps have been added but prior to dicing. This support coating or underfill layer provides added strength to the eventual reflowed solder connections, such that the operational lifetime of these connections is increased with respect to failure due to temperature cycling.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 9, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Hau Nguyen, Nikhil K. Kelkar, Shahram Mostafazadeh
  • Ferroelectric capacitor
    Patent number: 7423308
    Abstract: A ferroelectric capacitor includes a lower electrode, a ferroelectric film provided over the lower electrode and having a perovskite-type structure and an upper electrode provided over the ferroelectric film. The ferroelectric film includes a first ferroelectric film part having a first crystal system and formed along at least one interface with at least one of the lower electrode and the upper electrode and a second ferroelectric film part having a second crystal system that is different from the first crystal system.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: September 9, 2008
    Assignee: Fujitsu Limited
    Inventors: Masaki Kurasawa, Kenji Maruyama