Patents Examined by Hoang-Quan Ho
  • Vertical memory devices and methods of manufacturing the same
    Patent number: 9780096
    Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yong Park, Kee-jeong Rho, Hyeong Park, Tae-wan Lim
  • Display device
    Patent number: 9779652
    Abstract: A sub-pixel is provided in a display area of an organic EL display device. A bank layer surrounds an outer periphery of the sub-pixel. A contact area is positioned in the display area and is adjacent to the sub-pixel through the bank layer. A pixel electrode is provided in the sub-pixel. A common electrode is disposed across the sub-pixel and the contact area. At least a part of an auxiliary conductive layer is positioned in the contact area. A contact hole is provided in the contact area and electrically connects the common electrode and the auxiliary conductive layer.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 3, 2017
    Assignee: Japan Display Inc.
    Inventors: Kenta Kajiyama, Toshihiro Sato
  • Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs
    Patent number: 9761498
    Abstract: An integrated circuit included n-type FinFETs in an n-region and p-type FinFETs in a p-region. The integrated circuit includes: an n-type fin in the n-region comprising a silicon (Si) fin portion disposed on an oxidized fin portion, the Si fin portion consisting essentially of Si, and the oxidized fin portion consisting essentially of Si, germanium (Ge) and oxygen; and a p-type fin in the p-region consisting essentially of Si and Ge.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Alexander Reznicek, Joshua M. Rubin, Tenko Yamashita
  • Manufacturing method for solid-state imaging device and solid-state imaging device
    Patent number: 9754995
    Abstract: A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element including a second principal surface having an electrode arranged thereon, and a photoelectric converter part configured to photoelectrically convert the incident energy line so as to generate a signal charge; a second step of preparing a support substrate, provided with at least one through hole extending in a thickness direction thereof, having a third principal surface; a third step of aligning the imaging element and the support substrate with each other so that the one electrode is exposed out of the one through hole while the second and third principal surfaces oppose each other and joining the imaging element and the support substrate to each other; and a fourth step of embedding a conductive member in the through hole after the third step.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: September 5, 2017
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yasuhito Yoneta, Ryoto Takisawa, Shingo Ishihara, Hisanori Suzuki, Masaharu Muramatsu
  • Photodetector with plasmonic structure and method for fabricating the same
    Patent number: 9722108
    Abstract: A photodetector with a plasmon structure includes a semiconductor substrate, a plurality of light-receiving elements that are formed in a predetermined pattern, protruding from the semiconductor substrate, and a nanostructure that is placed in contact with a surface of the semiconductor substrate among the light-receiving elements and which induces a plasmon phenomenon thereon.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 1, 2017
    Assignee: AGENCY FOR DEFENSE DEVELOPMENT
    Inventors: Chulkyun Seok, Euijoon Yoon, Yongjo Park, Chiyeon Kim
  • Wafer backside interconnect structure connected to TSVs
    Patent number: 9716074
    Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Shau-Lin Shue
  • III-V field effect transistor on a dielectric layer
    Patent number: 9704958
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Edward William Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Light-emitting device
    Patent number: 9705040
    Abstract: A light-emitting device includes: a substrate; a light-emitting structure including first and second nitride-based semiconductor layers on the substrate and an active layer between the first and second nitride-based semiconductor layers; an insulating layer on a top surface of the light-emitting structure; a protrusion on the insulating layer, a top surface of the protrusion being larger than a bottom surface thereof, the protrusion having a trapezoidal cross-section; a transparent conductive layer covering a top surface of the light-emitting structure, a top surface of the insulating layer, and the top surface of the protrusion and having a constant thickness along the top surface of the light-emitting structure, the top surface of the insulating layer, and the top surface of the protrusion; and an electrode covering at least one of inclined surfaces of the protrusion on the transparent conductive layer.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-hoon Ha, Sang-yeob Song, Gi-bum Kim, Jae-in Sim, Seung-woo Choi
  • Germanium FinFETs with metal gates and stressors
    Patent number: 9698060
    Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann
  • Light emitting diode
    Patent number: 9698350
    Abstract: The disclosure relates to a light emitting diode. The light emitting diode includes a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode, a second electrode and a nanotube film. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked with each other in that order. The first electrode is electrically connected with the second semiconductor layer. The second electrode is electrically connected with the first semiconductor layer. The nanotube film is located on one of the first semiconductor layer, the active layer and the second semiconductor layer. The nanotube film comprises a number of nanotubes orderly arranged and combined with each other by ionic bonds.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: July 4, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Chip package and method of manufacturing the same
    Patent number: 9698086
    Abstract: Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: July 4, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Tyrone Jon Donato Soller
  • Memory device containing stress-tunable control gate electrodes
    Patent number: 9698223
    Abstract: A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, electrically conductive layers are formed in the backside recesses. Each electrically conductive layer includes a combination of a tensile-stress-generating metallic material and a compressive-stress-generating metallic material. The tensile-stress-generating metallic material may be ruthenium and the compressive-stress-generating metallic material may be tungsten. An anneal may be performed to provide an alloy of the compressive-stress-generating metallic material and the tensile-stress-generating metallic material.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 4, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, George Matamis
  • Graphene transistors on microbial cellulose
    Patent number: 9679970
    Abstract: A device including a biopolymer membrane, a passivation layer on the biopolymer membrane, a graphene layer on the passivation layer, a source electrode on the graphene layer, and a drain electrode on the graphene layer, wherein the graphene layer extends between the source electrode and the drain electrode.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 13, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Kyung-Ah Son, Baohua Yang, Hwa Chang Seo, Danny Wong, Jeong-Sun Moon
  • Metal gate structure with multi-layer composition
    Patent number: 9679984
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a gate stack disposed on the semiconductor substrate. The gate stack includes a high-k dielectric material layer, a titanium-rich TiN layer over the high-k dielectric layer, and a metal layer disposed over the titanium-rich TiN layer. The metal layer includes aluminum.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chin Chung, Shiang-Rung Tsai, Hsien-Ming Lee, Cheng-Lung Hung, Hsiao-Kuan Wei
  • Planarization method, method for manufacturing semiconductor structure, and semiconductor structure
    Patent number: 9679782
    Abstract: A planarization method includes at least two steps. One of the steps is to implant at least one impurity into a wafer to form a polish stop layer in the wafer. The other one of the steps is to polish a top surface of the wafer until reaching the polish stop layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ting Yen, Ying-Ho Chen
  • SiC epitaxial wafer and method for manufacturing the same
    Patent number: 9679767
    Abstract: Provided is a method of manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a SiC substrate using a SiC-CVD furnace which is installed in a glove box. The method includes a SiC substrate placement step of placing the SiC substrate in the SiC-CVD furnace while circulating gas in the glove box.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: June 13, 2017
    Assignee: SHOWA DENKO K.K.
    Inventors: Akira Miyasaka, Yutaka Tajima, Yoshiaki Kageshima, Daisuke Muto, Kenji Momose
  • Integrated circuit transistor structure with high germanium concentration SiGe stressor
    Patent number: 9660082
    Abstract: An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Jeff J. Xu, Chien-Hsun Wang, Chih Chieh Yeh, Chih-Hsiang Chang
  • Electrostatic discharge protection semiconductor device
    Patent number: 9653450
    Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The first doped region is electrically connected to a ground potential.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: May 16, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
  • Display panel
    Patent number: 9640562
    Abstract: A display panel is disclosed and includes an active area and a non-active area. A first, a second, a third, a fourth, a fifth, and a sixth charging scanning lines and a first, a second, a third, a fourth, a fifth, and a sixth charge-sharing scanning lines of an array unit on the active area are connected to a first, a second, a third, a fourth, a fifth, and a sixth pixel row, respectively. A first, a second, and a third detection lines on the non-active area are connected to the active area.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 2, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Zui Wang, Jinbo Guo
  • Adhesive film and manufacturing method of the same, and display device including the adhesive film
    Patent number: 9637665
    Abstract: An adhesive film that includes a first region having a first hardness, and second regions disposed on opposing sides of the first region and having a second hardness that is greater than the first hardness.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: May 2, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jin Bo Shim