Patents Examined by Hoang-Quan Ho
  • Packaging device and manufacturing method thereof
    Patent number: 10685904
    Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: June 16, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hsin-Chang Tsai, Chia-Yen Lee, Peng-Hsin Lee
  • Vertical field effect transistor including integrated antifuse
    Patent number: 10679998
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Vertical field effect transistor including integrated antifuse
    Patent number: 10680000
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Pixel structure, array substrate, liquid crystal display panel and pixel structure manufacture method
    Patent number: 10665720
    Abstract: The present invention provides a pixel structure, an array substrate, a liquid crystal display panel and a pixel structure manufacture method. The pixel structure includes a pixel electrode layer and a thin film transistor. The thin film transistor includes a gate, a source and a drain which are isolated with the gate and an organic semiconductor layer. The pixel structure further includes an Indium Tin Oxide layer and a metal layer, and the metal layer is located on a portion of the ITO layer. The source, the drain are formed on the ITO layer. A pattern formed by the organic semiconductor layer is electrically coupled to the ITO layer and the metal layer, and the pixel electrode layer is electrically coupled to the metal layer and the ITO layer.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: May 26, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Mian Zeng
  • Semiconductor device, manufacturing method thereof, and electronic device
    Patent number: 10658389
    Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 19, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Katsuaki Tochibayashi, Tomoaki Moriwaka, Jiro Nishida, Hidekazu Miyairi, Shunpei Yamazaki
  • Manufacturing method and structure of oxide thin film transistor
    Patent number: 10629745
    Abstract: The present invention provides a manufacture method and a structure of an oxide thin film transistor. The manufacture method of the structure of the oxide thin film transistor comprises providing a carrier; forming an oxide semiconducting layer (4); forming an etching stopper layer (5); forming two vias (51, 53) in the etching stopper layer (5) to expose the oxide semiconducting layer (4); removing a skin layer of the oxide semiconducting layer (4) in the two vias (51, 53) to form two recesses (41, 43) respectively connecting the two vias (51, 53); forming a source (61) and a drain (63) on the etching stopper layer (5), and the source (61) fills one via (51) and the recess (41) connecting therewith, and the drain (63) fills the other via (53) and the recess (43) connecting therewith; performing a post process.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: April 21, 2020
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Yutong Hu, Chihyuan Tseng, Chihyu Su, Wenhui Li, Xiaowen Lv, Longqiang Shi, Hejing Zhang
  • Schottky barrier diode
    Patent number: 10600874
    Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: March 24, 2020
    Assignee: TAMURA CORPORATION
    Inventors: Masaru Takizawa, Akito Kuramata
  • Contact module for optimizing emitter and contact resistance
    Patent number: 10580689
    Abstract: An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact via to a first portion of a first device. The method further includes filling the first contact via with metal material to form a first metal contact to the first portion of the first device. The method further includes forming additional contact vias to other portions of the first device and contacts of a second device. The method further includes cleaning the additional contact vias while protecting the first metal contact of the first portion of the first device. The method further includes filling the additional contact vias with metal material to form additional metal contacts to the other portions of the first device and the second device.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James W. Adkisson, Anthony K. Stamper
  • Semiconductor packages and methods of forming same
    Patent number: 10529698
    Abstract: An embodiment is a package including a first package structure. The first package structure includes a first integrated circuit die having an active side and a back-side, the active side comprising die connectors, a first electrical connector adjacent the first integrated circuit die, an encapsulant laterally encapsulating the first integrated circuit die and the first electrical connector, a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector, and thermal elements on the back-side of the first integrated circuit die. The package further includes a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Han-Ping Pu
  • Phase change memory array with integrated polycrystalline diodes
    Patent number: 10256271
    Abstract: A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Chung H. Lam, Fabio Carta, Matthew J. BrightSky
  • Vertical transistor with variable gate length
    Patent number: 10236214
    Abstract: A method of forming a vertical transistor includes forming a first pair of fins on a substrate; forming a second pair of fins on the substrate; forming a first trench in the substrate and interposed between each one of the first pair of fins; forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench; forming a first semiconductor structure interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region; and forming a second semiconductor structure interposed between each one of the second pair of fins, the second semiconductor structure having a first gate region interposed between a second source region and a second drain region.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Vertical field effect transistor including integrated antifuse
    Patent number: 10229919
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Film forming method, method of manufacturing semiconductor light-emitting device, semiconductor light-emitting device, and illuminating device
    Patent number: 10224463
    Abstract: An object of the present invention is to provide a film formation technique having high productivity by realizing a foundation layer having excellent crystallinity with a small film thickness of about 2 ?m. An embodiment of the present invention relates to a film forming method which includes the step of forming a buffer layer by sputtering on a sapphire substrate held by a substrate holder. The buffer layer includes an epitaxial film having a wurtzite structure prepared by adding at least one substance selected from the group consisting of C, Si, Ge, Mg, Zn, Mn, and Cr to AlxGa1?xN (where 0?x?1).
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: March 5, 2019
    Assignee: CANON ANELVA CORPORATION
    Inventor: Yoshiaki Daigo
  • Electrostatic discharge protection semiconductor device
    Patent number: 10204897
    Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
  • SiC epitaxial wafer and method for manufacturing the same
    Patent number: 10176987
    Abstract: A SiC epitaxial wafer including: a SiC epitaxial layer that is formed on a SiC substrate having an off angle, wherein the surface density of triangular defects, in which a distance from a starting point to an opposite side in a horizontal direction is equal to or greater than (a thickness of the SiC epitaxial layer/tan(x))×90% and equal to or less than (the thickness of the SiC epitaxial layer/tan(x))×110%, in the SiC epitaxial layer is in the range of 0.05 pieces/cm2 to 0.5 pieces/cm2 (where x indicates the off angle).
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: January 8, 2019
    Assignee: SHOWA DENKO K.K.
    Inventors: Akira Miyasaka, Yutaka Tajima, Yoshiaki Kageshima, Daisuke Muto, Kenji Momose
  • Vertical transistors with buried metal silicide bottom contact
    Patent number: 10170575
    Abstract: A method of fabricating the vertical field effect transistor includes forming a dielectric layer on a metal semiconductor alloy layer that is present on a substrate of a semiconductor material. The dielectric layer is bonded to a supporting substrate. The substrate of the semiconductor material is cleaved, wherein a remaining portion of the semiconductor material provides a semiconductor surface layer in direct contact with the metal semiconductor alloy layer. A vertical fin type field effect transistor (FinFET) is formed atop the stack of the semiconductor surface layer, the metal semiconductor alloy layer, the dielectric layer and the supporting substrate, wherein the semiconductor surface layer provides at least one of a source region or a drain region of the FinFET and the metal semiconductor alloy provides a contact to the source region or the drain region of the FinFET.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Tak H. Ning, Alexander Reznicek
  • Superconductor device interconnect
    Patent number: 10158062
    Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: December 18, 2018
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Christopher F. Kirby, Michael Rennie, Aurelius L. Graninger
  • Anti-fuse nonvolatile memory devices employing lateral bipolar junction transistors as selection transistors
    Patent number: 10115729
    Abstract: An anti-fuse nonvolatile memory device includes an anti-fuse memory cell and a bipolar junction transistor. The anti-fuse, memory cell has a first terminal and a second terminal. The second terminal is coupled to a word line. The bipolar junction transistor has a collector terminal coupled to the first terminal of the anti-fuse, memory cell, a base terminal, and an emitter terminal coupled to a bit line.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 30, 2018
    Assignee: SK Hynix Inc.
    Inventor: Kwang II Choi
  • Repair structure of line defect of AMOLED display panel and repair method
    Patent number: 10109688
    Abstract: The present invention provides a repair structure of a line defect of an AMOLED display panel and a repair method. The conductive film (410) correspondingly overlaps and covers above the test TFT (310) and is insulated from the test TFT (310), and the repair line (420) is insulated and crossed with all the signal fanout lines (200) and the corresponding test line (330). It is realized that the repair line is directly grafted on the AMOLED display panel detecting circuit, which can utilize the present detecting circuit layout of the AMOLED display panel capable of introducing the repair line for having the repair function and saving the layout space, and has no additional requirement to the control IC, and particularly, can be applicable for the line defect repair of the small size, high resolution AMOLED display panel.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 23, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Baixiang Han
  • Power module, power converter and manufacturing method of power module
    Patent number: 10104797
    Abstract: A power module includes a heat-dissipating substrate, a first planar power device and a second planar power device. The first planar power device includes a plurality of electrodes disposed on an upper surface of the first planar power device. The second planar power device includes a plurality of electrodes disposed on an upper surface of the second planar power device. Lower surfaces of the first planar power device and the second planar power device are disposed on the heat-dissipating substrate.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 16, 2018
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventor: Jian-Hong Zeng