Patents Examined by Hoang-Quan Ho
  • Through-substrate via structure and method of manufacture
    Patent number: 10079199
    Abstract: A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: September 18, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Semiconductor device and fabricating method thereof
    Patent number: 10050030
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Back surface radiation type image sensor, imaging device, and electronic apparatus
    Patent number: 10050077
    Abstract: A device including a substrate and an imaging element layer having a plurality of imaging elements is provided, where the imaging element layer is located between the substrate and a wiring layer having a plurality of wiring lines (41), and wiring lines of the wiring layer are arranged in pixel regions (Z) configured to receive light having a wavelength less than a predetermined wavelength (B, G). Accordingly, by more uniformly distributing the wiring layer throughout, it is possible to reduce an unevenness that occurs at a polishing film. Moreover, because wiring lines are not disposed in pixel regions (Z) configured to receive light having a wavelength greater than the predetermined wavelength (R), irregularities may be reduced.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: August 14, 2018
    Assignee: Sony Corporation
    Inventor: Tadahiro Hagita
  • Differential temperature sensor
    Patent number: 10038133
    Abstract: Sensor including a substrate, an assembly of thermoelectric layers including at least one first and one second junction of a thermocouple, at least one first and one second connection pads arranged to transfer heat respectively to each first and each second junction, a support member (2) of the substrate (3) intended to be connected to the hot source (Sc) and to the cold source (Sf), first and second metal connectors arranged to electrically connect the support member (2) respectively to each first and each second connection pad, the support member (2) including a thermal conductor configured to transfer heat from the hot source (Sc) to the first metal connector, and to transfer heat from the second metal connector to the cold source (Sf).
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 31, 2018
    Assignees: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, HOTBLOCK ONBOARD
    Inventors: Guillaume Savelli, Joël Dufourcq
  • Manufacture method of TFT substrate and manufactured TFT substrate
    Patent number: 10038074
    Abstract: The present invention provides a manufacture method of a TFT substrate and a manufactured TFT substrate. By locating the first channel region and the first lightly doped offset region between the first source and the drain, and locating the second channel region and the second lightly doped offset region between the second source and the drain, and forming the first overlapping region and the second overlapping region respectively between the drain and the gate and between the second source and the gate, thus, the paths of the current flowing from the first, the second sources to the drain and the current flowing from the drain to the first, the second sources are the same. Namely, the current path from source to the drain and the current path from the drain to the source are the same. According, the symmetry of the TFT structure is realized.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 31, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Shipeng Chi
  • Light-emitting device and method for producing light-emitting device
    Patent number: 10038124
    Abstract: Provided is a light-emitting device that has excellent light extraction efficiency, inhibits deterioration of light-emission characteristics over time, and can be easily produced. The light-emitting device includes a substrate, a solid-state light-emitting element mounted on the substrate, a circular tube-shaped member positioned on the substrate such as to surround the solid-state light-emitting element, and a transparent resin portion including a cylindrical section that encapsulates the solid-state light-emitting element and that is in contact with an inner surface of the circular tube-shaped member, and a dome-shaped section that is positioned above the cylindrical section. The inner surface of the circular tube-shaped member is water repellent. The dome-shaped section contains a phosphor that is excited by light of a light-emission wavelength of the solid-state light-emitting element.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 31, 2018
    Assignee: Dexerials Corporation
    Inventor: Takehiro Yamasuge
  • III-V field effect transistor on a dielectric layer
    Patent number: 10014377
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Edward William Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • LTPS TFT array substrate, its manufacturing method, and display device
    Patent number: 10008516
    Abstract: The present disclosure relates to the field of TFT manufacturing process, and provides an LTPS TFT array substrate, its manufacturing method and a display device. The LTPS TFT array substrate includes contact holes through which a source electrode and a drain electrode of the array substrate are connected to an active layer, respectively, wherein a conductive pattern connected to the active layer is provided at a base portion of the contact hole. According to the present disclosure, it is able to form an excellent ohmic contact between the source/drain electrodes and the active layer after the contact holes have been etched, thereby to ensure the display quality of the display device.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: June 26, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yueping Zuo, Zheng Liu
  • Low-temperature polysilicon thin film transistor array substrate and method of fabricating the same, and display device
    Patent number: 10002889
    Abstract: The present invention provides a low-temperature polysilicon thin film transistor array substrate and a method of fabricating the same, and a display device. The array substrate comprises: a substrate; a polysilicon active layer provided on the substrate; a first insulation layer provided on the active layer; a plurality of gates and a gate line provided on the first insulation layer; a second insulation layer provided on the gates; a source, a drain, a data line and a pixel electrode electrically connected with the drain, which are provided on the second insulation layer, the source covers the plurality of gates. The plurality of gates are provided directly below the source, so that the leakage current is reduced and the aperture ratio of panel is improved.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: June 19, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jiaxiang Zhang, Xiaohui Jiang, Changjiang Yan
  • Superconductor device interconnect
    Patent number: 10003005
    Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: June 19, 2018
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Christopher F. Kirby, Michael Rennie, Aurelius L. Graninger
  • Monolithic integration of III-V cells for powering memory erasure devices
    Patent number: 9997475
    Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kenneth Rodbell, Davood Shahrjerdi
  • Light-emitting device
    Patent number: 9997679
    Abstract: A light-emitting device of the invention includes, a first substrate; a light-emitting element mounted on the first substrate and includes a second substrate and a semiconductor structure including a light-emitting layer; and a light-shielding body which is formed only on a surface of the light-emitting element opposite to the first substrate and includes a material including light-shielding particles.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: June 12, 2018
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Tsutomu Okubo
  • Organic light-emitting diode display having high aperture ratio and method for manufacturing the same
    Patent number: 9997581
    Abstract: An organic light-emitting diode display includes a substrate in which an emission area and a non-emission area are defined; a thin film transistor disposed in the non-emission area on the substrate; passivation layer disposed on the thin film transistor; a first storage capacitor electrode and a second storage capacitor electrode superposed thereon, having the passivation layer interposed therebetween, in the emission area; an overcoat layer disposed on the second storage capacitor electrode; and an anode disposed on the overcoat layer, coming into contact with one side of the second storage capacitor electrode through an overcoat layer contact hole penetrating the overcoat layer and, coming into contact with part of the thin film transistor through a passivation layer contact hole disposed in the overcoat layer contact hole and penetrating the passivation layer.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: June 12, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Yongmin Kim, Jeongoh Kim, Jungsun Beak, Kyoungjin Nam, Jeonggi Yun
  • Semiconductor device and method of manufacturing the same
    Patent number: 9985149
    Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 29, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Metal trench de-noise structure and method for forming the same
    Patent number: 9978638
    Abstract: A metal trench de-noise structure includes a trench disposed in a substrate, an insulating layer deposited on the sidewall of the trench, an Inter-Layer Dielectric layer covering the substrate and the insulating layer, and a metal layer penetrating the Inter-Layer Dielectric layer to fill up the trench. The metal layer may be grounded or floating.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: May 22, 2018
    Assignee: Realtek Semiconductor Corp.
    Inventor: Ta-Hsun Yeh
  • Wafer backside interconnect structure connected to TSVs
    Patent number: 9978708
    Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Shau-Lin Shue
  • Use of dielectric film to reduce resistivity of transparent conductive oxide in nanowire LEDs
    Patent number: 9972750
    Abstract: Various embodiments include methods of fabricating light emitting diode (LED) devices, such as nanowire LED devices, that include forming a layer of a transparent, electrically conductive material over at least a portion of a non-planar surface of an LED device, and depositing a layer of a dielectric material over at least a portion of the layer of transparent conductive material, wherein depositing the layer of dielectric material comprises at least one of: (a) depositing the layer using a chemical vapor deposition (CVD) process, (b) depositing the layer at a temperature of 200° C. or more, and (c) depositing the layer using one or more chemically active precursors for the dielectric material.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: May 15, 2018
    Assignee: GLO AB
    Inventors: Scott Brad Herner, Daniel Bryce Thompson
  • Multiple-step epitaxial growth S/D regions for NMOS FinFET
    Patent number: 9966433
    Abstract: A method of forming NFET S/D structures with multiple layers, with consecutive epi-SiP layers being doped at increasing dosages of P and the resulting device are provided. Embodiments include forming multiple epi-Si layers in each S/D cavity of a NFET; and performing in-situ doping of P for each epi-Si layer, wherein consecutive epi-Si layers are doped at increasing dosages of P.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: May 8, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhiqing Li, Shesh Mani Pandey, Francis Benistant
  • Laser assisted SiC growth on silicon
    Patent number: 9960037
    Abstract: A method for forming a compound on a substrate is provided. The method includes depositing a composition onto a surface of a substrate; illuminating the composition and the substrate with pulsed energy; melting the substrate and decomposing the composition simultaneously; and forming a compound on the substrate. A first component of the compound is derived from the substrate and a second component of the compound is derived from the composition.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: May 1, 2018
    Assignee: Board Of Trustees Of Michigan State University
    Inventors: Premjeet Chahal, Tim Hogan, Amanpreet Kaur
  • Light emitting device and method for manufacturing the same
    Patent number: 9935249
    Abstract: Provided is a light emitting device that includes a plurality of light-emitting elements, a fluorescent layer that is disposed on or above the plurality of light-emitting elements, and light blocking layers that are disposed in the fluorescent layer, two of the light blocking layers being disposed, when an adjacent two of the plurality of light-emitting elements are seen, at positions each of which is closer than the center of a region between the two light-emitting elements to the center of one of the two light-emitting elements while the center of the region between the two light-emitting elements functions as a reference.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: April 3, 2018
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Satoshi Tanaka