Abstract: The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic device capable of further improving quality. A flattening film is formed so as to fill a recessed portion of a semiconductor substrate having a pixel region in which a plurality of pixels is arranged in an array, a recessed region is formed in the flattening film by hollowing out a region corresponding to the pixel region, and a color filter layer is formed in the recessed region. In addition, an on-chip lens layer is formed on a plane including the flattening film and the color filter layer. The present technology is applicable, for example, to a CMOS image sensor.

Abstract: A semiconductor device may include a first insulated substrate, a first semiconductor chip and a second semiconductor chip disposed on the first insulated substrate, a second insulated substrate opposed to the first insulated substrate with the first semiconductor chip interposed therebetween, and a third insulated substrate opposed to the first insulated substrate with the second semiconductor chip interposed therebetween and located side by side with the second insulated substrate.

Abstract: Provided is a method of producing an array substrate. This method of producing an array substrate has following steps: forming a passivation layer on a base substrate; forming a photoresist layer on the passivation layer, and performing a patterning process on the photoresist layer to form a photoresist mask having an opening pattern; introducing an etching resistant layer precursor material to the passivation layer by ion injection through the opening pattern; generating plasma by using an etching gas, etching the passivation layer by using the plasma through the opening pattern to form a via hole penetrating the passivation layer; and peeling the photoresist mask. Also provided are an array substrate and a display apparatus.

Abstract: A light-emitting diode (LED) chip with reflective layers having high reflectivity. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer.

Abstract: Interconnect structures and processes of fabricating the interconnect structures generally includes a recessed metal conductor and a discontinuous capping layer thereon. The discontinuous “capped” metal interconnect structure provides improved performance and reliability for the semiconductor industry.

Abstract: A semiconductor structure comprising III-N materials, includes: a support substrate; a main layer of III-N material, the main layer comprising a first section disposed on the support substrate and a second section disposed on the first section; an inter-layer of III-N material, disposed between the first section and the second section in order to compress the second section of the main layer, wherein the structure's inter-layer consists of a lower layer disposed on the first section and an upper layer disposed on the lower layer and formed by a superlattice.

Abstract: In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

Abstract: A device that is a combination of a superconducting nanowire single-photon detector and a superconducting multi-level memory. These devices can be used to count a number of photons impinging on the device through single-photon to single-flux conversion. Electrical characterization of the device demonstrates single-flux quantum (SFQ) separated states. Optical measurements using attenuated laser pulses with different mean photon number, pulse energies and repetition rates are shown to differentiate single-photon detection from other possible phenomena, such as multiphoton detection and thermal activation. Array devices and methods are also discussed.

Abstract: According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

Abstract: Interconnect structures and processes of fabricating the interconnect structures generally includes a recessed metal conductor and a discontinuous capping layer thereon. The discontinuous “capped” metal interconnect structure provides improved performance and reliability for the semiconductor industry.

Abstract: The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.

Abstract: A display device includes a substrate, a plurality of pixels on the substrate, a first electrode arranged for each pixel on the substrate, a pixel defining layer on the substrate along a boundary of each pixel and including an opening exposing the first electrode of the pixel, an organic layer on the first electrode in the opening of the pixel defining layer, and a second electrode on the organic layer, the pixel defining layer including a first pixel defining layer and a second pixel defining layer stacked on a surface of the first pixel defining layer, the surface of the first pixel defining layer including an upper surface and a side surface, and a surface roughness of the upper surface of the first pixel defining layer being greater than a surface roughness of the first electrode.

Abstract: Methods for forming semiconductor structures are disclosed herein. An exemplary method includes forming a gate structure having a dummy gate stack over a substrate, performing a gate replacement process, such that the dummy gate stack is replaced with a metal gate stack, and forming a non-silane based oxide capping layer over the gate structure. The gate replacement process includes removing a portion of the dummy gate stack from the gate structure, thereby forming a gate trench. A work function layer is formed in the gate trench, a blocking layer is formed in the gate trench over the work function layer, and a metal layer (including, for example, aluminum) is formed in the gate trench over the blocking layer. The blocking layer includes titanium and nitrogen with a titanium to nitrogen ratio that is greater than one. In some implementations, the work function layer is formed over a dielectric layer.

Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, a fin over the substrate and the isolation structure, a gate structure engaging a first portion of the fin, first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin, source/drain (S/D) features adjacent to the first sidewall spacers, and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers and the second portion of the fin include a same dopant.

Abstract: A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.

Abstract: A light emitting device includes a light emitting element that emits a light having a peak emission wavelength in a wavelength range of not less than 410 nm and not more than 425 nm, and a phosphor emitting a fluorescence having a peak at a longer wavelength side than the peak emission wavelength of light emitted from the light emitting element. A general color rendering index Ra of fluorescence emitted from the phosphor is not less than 95. A general color rendering index Ra of mixed light of light emitted from the light emitting element and fluorescence emitted from the phosphor is higher than a general color rendering index Ra of fluorescence emitted from the phosphor. A color rendering index Rf of the mixed light is not less than 96.

Abstract: Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.

Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.

Abstract: A surface plasmon-semiconductor heterojunction resonant optoelectronic device and a preparation method thereof are provided. A surface ligand molecule is modified on a plasmonic nanostructure, a plasmonic crystal face structure is bound to the surface ligand molecule, a semiconductor nanostructure seed crystal is located on the plasmonic crystal face structure, a one-dimensional semiconductor nanostructure is located on the semiconductor nanostructure seed crystal, and all parts are in tight contact. The heterogeneous integration material achieves a lattice match at an interface, greatly reduces a loss caused by defects and rough crystal faces, and can achieve direct coupling of a surface plasmon mode and an optical mode. The heterogeneous integration material has a large application prospect in the fields of a nanolaser, a nano heat source and photoelectric detection and photocatalysis.