Patents Examined by Hsin-Yi Hsieh
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Patent number: 10886436Abstract: A light-emitting device may include a light-emitting structure, a first electrode formed on the first conductive semiconductor layer, and a second electrode formed on the second conductive semiconductor layer. The first electrode may include a first pad, and a first branch coupled to the first pad and extending in a longitudinal direction. The second electrode may include a second pad, and a third branch and a fourth branch that are connected to the second pad and extend from the second pad.Type: GrantFiled: May 16, 2011Date of Patent: January 5, 2021Assignee: LG INNOTEK CO., LTD.Inventors: MinGyu Na, SungKyoon Kim, SungHo Choo, WooSik Lim
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Patent number: 10886196Abstract: Semiconductor devices having a conductive via and methods of forming the same are described herein. As an example, a semiconductor devices may include a conductive via formed in a substrate material, a barrier material, a first dielectric material on the barrier material, a coupling material formed on the substrate material and on at least a portion of the dielectric material, a second dielectric material formed on the coupling material, and an interconnect formed on the conductive via.Type: GrantFiled: April 1, 2019Date of Patent: January 5, 2021Assignee: Micron Technology, Inc.Inventor: Jaspreet S. Gandhi
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Patent number: 10879322Abstract: A pixel definition layer is provided. The pixel definition layer includes: a base definition layer having a plurality of openings for defining pixel regions, and a first definition leer arranged on a side surface of at least one of the openings of the base definition layer, and a hydrophilic property of the base definition layer is different from a hydrophilic property of the first definition layer.Type: GrantFiled: November 24, 2017Date of Patent: December 29, 2020Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Wenjun Hou
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Patent number: 10872885Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.Type: GrantFiled: April 6, 2018Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho
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Patent number: 10861710Abstract: A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.Type: GrantFiled: October 1, 2018Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Ming-Tan Lee, Chen-Cheng Kuo, De-Yuan Lu
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Patent number: 10854615Abstract: A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.Type: GrantFiled: March 30, 2018Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun Po Chang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Wei-Yang Lee, Tzu-Hsiang Hsu
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Patent number: 10854774Abstract: A lift-off method transfers onto a transfer substrate an optical device layer of an optical device wafer in which the optical device layer is formed over a front surface of an epitaxy substrate through a GaN buffer layer. The lift-off method includes: bonding the transfer substrate onto a front surface of the optical device layer through a bonding layer to form a composite substrate; applying a pulsed laser beam of such a wavelength as to be transferred through the epitaxy substrate constituting the composite substrate but to be absorbed in the buffer layer from a back surface side of the epitaxy substrate, to break the buffer layer; and peeling the optical device layer from the epitaxy substrate and transferring the optical device layer onto the transfer substrate, after the buffer layer breaking step is performed.Type: GrantFiled: October 12, 2018Date of Patent: December 1, 2020Assignee: DISCO CORPORATIONInventors: Tasuku Koyanagi, Hiroki Takeuchi
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Patent number: 10851470Abstract: A silicon carbide crystal and a method for manufacturing the same are disclosed. The silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low concentration. Therefore, the crystal defects can be significantly reduced.Type: GrantFiled: March 30, 2018Date of Patent: December 1, 2020Assignee: GLOBALWAFERS CO., LTD.Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, Man-Hsuan Lin
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Patent number: 10847627Abstract: A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.Type: GrantFiled: February 17, 2016Date of Patent: November 24, 2020Assignee: DYNAX SEMICONDUCTOR, INC.Inventors: Naiqian Zhang, Feihang Liu, Xin Jin, Yi Pei, Xi Song
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Patent number: 10840387Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.Type: GrantFiled: April 5, 2018Date of Patent: November 17, 2020Assignee: QUALCOMM IncorporatedInventors: Fabio Alessio Marino, Sinan Goktepeli, Narasimhulu Kanike, Qingqing Liang, Paolo Menegoli, Francesco Carobolante, Aristotele Hadjichristos
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Patent number: 10840463Abstract: According to one embodiment, a display device includes an insulating substrate including a first main surface, a first supporting substrate adhered to the first main surface of the insulating substrate, and a second supporting substrate spaced from the first supporting substrate and adhered to the first main surface of the insulating substrate, and the first supporting substrate includes a first side surface opposing the second supporting substrate, the second supporting substrate includes a second side surface opposing the first supporting substrate, the first supporting substrate is formed into a tapered shape which narrows toward the first side surface, and the second supporting substrate is formed into a tapered shape which narrows toward the second side surface.Type: GrantFiled: February 22, 2018Date of Patent: November 17, 2020Assignee: Japan Display Inc.Inventors: Takumi Sano, Yasushi Kawata
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Patent number: 10840158Abstract: A pixel structure includes at least one sub-pixel. The sub-pixel includes a substrate, a first micro light-emitting element, a repair micro light-emitting element, a first connecting line, a second connecting line, and a bridge pattern. The first micro light-emitting element is disposed on the substrate. The repair micro light-emitting element is disposed on the first micro light-emitting element and partially overlaps the first micro light-emitting element in a vertical direction of the substrate. The first connecting line is electrically connected to a first electrode of the first micro light-emitting element and a third semiconductor layer of the repair micro light-emitting element. The second connecting line is electrically connected to a second electrode of the first micro light-emitting element.Type: GrantFiled: December 3, 2018Date of Patent: November 17, 2020Assignee: AU OPTRONICS CORPORATIONInventors: Ting-Wei Guo, Cheng-Chieh Chang, Chen-Chi Lin, Yi-Cheng Liu
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Patent number: 10833083Abstract: Systems and methods according to one or more embodiments are provided for improved reliability and efficiency of high side power stage output drivers used in switching amplifiers. In one example, a system includes a power device structure comprising an nwell structure formed within a semiconductor p substrate and a pwell structure formed within the nwell structure. The system further includes one or more NMOS electronic power devices formed on the pwell structure and a pwell guardring formed on the pwell structure configured to surround the one or more NMOS electronic power devices. The system further includes an nwell guardring formed on the nwell structure configured to surround the pwell structure and a p+ guardring formed on the nwell structure configured to surround the nwell guardring.Type: GrantFiled: April 5, 2018Date of Patent: November 10, 2020Assignee: SYNAPTICS CORPORATIONInventor: Dan Shen
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Patent number: 10825730Abstract: A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element having a second principal surface having an electrode arranged thereon, and a photoelectric converter part configured to photoelectrically convert the incident energy line so as to generate a signal charge; a second step of preparing a support substrate, provided with a through hole extending in a thickness direction thereof, having a third principal surface; a third step of aligning the imaging element and the support substrate with each other so that the electrode is exposed out of the through hole while the second and third principal surfaces oppose each other and joining the imaging element and the support substrate to each other; and a fourth step of arranging a conductive ball-shaped member in the through hole and electrically connecting the ball-shaped member to the electrode after the third step.Type: GrantFiled: June 5, 2018Date of Patent: November 3, 2020Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Yasuhito Yoneta, Ryoto Takisawa, Shingo Ishihara, Hisanori Suzuki, Masaharu Muramatsu
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Patent number: 10818773Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.Type: GrantFiled: September 26, 2016Date of Patent: October 27, 2020Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC.Inventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie
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Patent number: 10811262Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.Type: GrantFiled: January 14, 2016Date of Patent: October 20, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Hsuan Lee, Jyh-Cherng Sheu, Sung-Li Wang, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong
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Patent number: 10811418Abstract: A dynamic random access memory (DRAM) cell array using facing bars and a method of fabricating the DRAM cell array are disclosed. A first DRAM cell and a second DRAM cell of each of DRAM cell pairs of a DRAM cell array fabricated using a method of fabricating a DRAM cell array share a facing bar and a bit line plug therebetween. Thus, the overall layout area is greatly reduced by a DRAM cell array fabricated using the method of fabricating the DRAM cell array. Further, in the method of fabricating the DRAM cell array, a storage of each of the DRAM cells of the DRAM cell array is formed as a multi-fin type having a plurality of lateral protrusions, thereby greatly increasing an area of the storage.Type: GrantFiled: April 11, 2018Date of Patent: October 20, 2020Assignee: DOSILICON CO., LTD.Inventors: Jin Ho Kim, Tae Gyoung Kang
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Patent number: 10804424Abstract: A method for manufacturing a light emitting element includes: forming a semiconductor structure on a first substrate; providing a second substrate configured to be bonded above a side of the semiconductor structure opposite the first substrate; forming a metal layer above at least one of (i) a side of the semiconductor structure opposite the first substrate, and/or (ii) a side of the second substrate that is to be located closer to the semiconductor structure; bonding the second substrate above the semiconductor structure via a bonding member; removing the first substrate from the semiconductor structure to obtain a bonded body in which the second substrate is bonded above the semiconductor structure; and singulating the bonded body.Type: GrantFiled: August 30, 2017Date of Patent: October 13, 2020Assignee: NICHIA CORPORATIONInventor: Eiji Muramoto
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Patent number: 10797154Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.Type: GrantFiled: June 23, 2016Date of Patent: October 6, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie
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Patent number: 10692848Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.Type: GrantFiled: February 8, 2016Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Chun Chuang, Yu-Chen Hsu, Hao Chun Liu, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen