Abstract: In an embodiment, a wide bandgap semiconductor power device, includes a wide bandgap semiconductor substrate layer; an epitaxial semiconductor layer disposed above the wide bandgap semiconductor substrate layer; a gate dielectric layer disposed directly over a portion of the epitaxial semiconductor layer; and a gate electrode disposed directly over the gate dielectric layer. The gate electrode includes an in-situ doped semiconductor layer disposed directly over the gate dielectric layer and a metal-containing layer disposed directly over the in-situ doped semiconductor layer.

Abstract: A semiconductor device includes a tube-like structure comprising a plurality of dielectric layers and conductor layers that are disposed on top of one another; a conductor tip integrally formed with a cap conductor layer that is disposed on a top surface of the tube-like structure, wherein the conductor tip extends to a central hole of the tube-like structure; and at least one photodetector formed within a bottom portion of the tube-like structure.

Abstract: A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A semiconductor device of the present invention includes: a plurality of wiring boards disposed separately from one another; a plurality of semiconductor elements disposed on first main surfaces of the wiring boards and electrically connected to the wiring boards; a plurality of terminals electrically connected to the wiring boards; a sealing resin sealing the wiring boards and the semiconductor elements so that second main surfaces of the wiring boards are exposed.

Abstract: An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.

Abstract: The nitride-based semiconductor device includes a carrier traveling layer 1 composed of non-doped AlxGa1-xN (0?X<1); a barrier layer 2 formed on the carrier traveling layer 1 and composed of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the carrier traveling layer 1; a threshold voltage control layer 3 formed on the barrier layer 2 and composed of a non-doped semiconductor having a lattice constant equal to that of the carrier traveling layer 1; and a carrier inducing layer 4 formed on the threshold voltage control layer 3 and composed of a non-doped or n-type semiconductor having a lattice constant smaller than that of the carrier traveling layer 1. The nitride-based semiconductor device further includes a gate electrode 5 formed in a recess structure, a source electrode 6 and a drain electrode 7.

Abstract: Provided is a heat-sink-attached power-module substrate, in which a metal layer and first layers are formed from aluminum sheets having a purity of 99.99 mass % or greater and a heat sink and second layers are formed from aluminum sheets having a purity lower than that of the metal layer and the first layers: when a thickness is t1 (mm), a joined-surface area is A1 (mm2), yield strength at 25° C. is ?11 (N/mm2), yield strength at 200° C. is ?12 (N/mm2) in the second layers; a thickness is t2 (mm), a joined-surface area is A2 (mm2), yield strength at 25° C. is ?21 (N/mm2), and yield strength at 200° C. is ?22 (N/mm2) in the heat sink.

Abstract: A thin film transistor and a method for manufacturing the same, an array substrate including the thin film transistor, and an electronic apparatus including the thin film transistor or provided with the array substrate. The thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, and a source electrode and a drain electrode, the active layer is formed of a mixture including a semiconductor nano-material and a photoresist material. The method for manufacturing the thin film transistor includes: preparing a mixture including a semiconductor nano-material and a photoresist material; applying the mixture over a substrate, and forming a patterned active layer by exposure and development.

Abstract: Microelectronic packages having hermetic cavities are provided, as are methods for producing such packages. In one embodiment, the microelectronic package includes a sensor die having first and second Microelectromechanical Systems (MEMS) transducer structures formed thereon. First and second cap pieces are coupled to the sensor die by, for example, direct or indirect bonding. A first hermetic cavity encloses the first MEMS transducer structure and is at least partially defined by the first cap piece and the sensor die. Similarly, a second hermetic cavity encloses the second MEMS transducer structure and at least partially defined by the second cap piece and the sensor die. A vent hole is fluidly coupled to the first hermetic cavity and is sealed by the second cap piece.

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.

Abstract: A gate trench and a protective trench are provided on a top surface of the silicon carbide semiconductor layer of a first conductivity type. A protective diffusion layer of a second conductivity type is provided at a position deeper than the gate electrode in the silicon carbide semiconductor layer. An inter-layer insulating film covers a surface of the gate electrode and includes a cell opening. A source electrode is electrically connected to the source region via the cell opening and electrically connected to the protective diffusion layer via the protective trench. A plated film is provided on the source electrode. A concave part is provided on a top surface of the source electrode above the protective trench. A depth in a vertical direction of the concave part is equal to or less than half of a width in a horizontal direction of the concave part.

Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: An infrared light-receiving device includes an optical absorption layer disposed on a principal surface of a substrate and an optical filter disposed on the optical absorption layer, the optical filter including first, second, and third semiconductor regions that are arranged in that order in a direction from the optical absorption layer to the optical filter, each of the first, second, and third semiconductor regions including an n-type InGaAs layer. The optical absorption layer includes a type-II superlattice structure. The first semiconductor region contains an n-type impurity with a concentration of 2.0×1019 cm?3 or more. The third semiconductor region contains an n-type impurity with a concentration of 3.0×1018 cm?3 or less and 8.0×1017 cm?3 or more. The second semiconductor region contains an n-type impurity with a concentration between the impurity concentration of the first semiconductor region and the impurity concentration of the third semiconductor region.

Abstract: An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 ?·cm.

Abstract: Apparatus and associate methods relate to a high-voltage MOSFET bounded by two trenches, each having dielectric sidewalls and a dielectric bottom isolating a top field plate and a bottom field plate. The top field plate is electrically connected to a biasing circuit net, and the bottom field plate is biased via a capacitive coupling to the top field plate. The upper field plate and lower field plate are configured to deplete the majority carriers in a drain region of the MOSFET bounded by the two trenches so as to equalize two local maxima of an electric field induced by a drain/body bias, the two local maxima located proximate a drain/body metallurgical junction and proximate a trench bottom. The two local maxima of the electric field are equalized by controlling a depth location of an intervening dielectric between the upper field plate and the lower field plate.

Abstract: A light receiving and emitting element module includes a wiring substrate; a light emitting element and a light receiving element which are disposed on the wiring substrate; and a lens member having a lens portion, a support portion configured to support the lens portion disposed above the light emitting element and the light receiving element and a column disposed on a lower surface of the support portion, wherein a tip end of the column is in contact with an upper surface of the wiring substrate.

Abstract: An avalanche photodiode detector is provided with a substrate including an array of avalanche photodiodes. An optical interface surface of the substrate is arranged for accepting external input radiation. There is provided at least one cross-talk blocking layer of material including apertures positioned to allow external input radiation to reach photodiodes and including material regions positioned for attenuating radiation in the substrate that is produced by photodiodes in the array. Alternatively at least one cross-talk blocking layer of material is disposed on the optical interface surface of the substrate to allow external input radiation to reach photodiodes and attenuate radiation in the substrate that is produced by photodiodes in the array. At least one cross-talk filter layer of material can be disposed in the substrate adjacent to the photodiode structures, including a material that absorbs radiation in the substrate that is produced by photodiodes in the array.

Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cells, a first film, and a second film. The memory cells are placed at intervals in a first direction on a semiconductor substrate. The first film is placed continuously in the first direction above the memory cells so as to cover all of the memory cells and including mainly metal oxide. The second film is placed on the first film and including mainly silicon nitride or silicon dioxide.

Abstract: A gate insulating film covers a trench penetrating through a source region and a body region and reaching a drift layer in each of a first cell region and a second cell region. The gate electrode is provided in the trench. A high-concentration layer of the first conductivity type is provided between the drift layer and the body region in the first cell region and has a second impurity concentration higher than the first impurity concentration. A current restriction layer is provided between the drift layer and the body region in the second cell region and has the first conductivity type and a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration.