Abstract: A silicon carbide crystal and a method for manufacturing the same are disclosed. The silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low concentration. Therefore, the crystal defects can be significantly reduced.

Abstract: A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.

Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.

Abstract: A pixel structure includes at least one sub-pixel. The sub-pixel includes a substrate, a first micro light-emitting element, a repair micro light-emitting element, a first connecting line, a second connecting line, and a bridge pattern. The first micro light-emitting element is disposed on the substrate. The repair micro light-emitting element is disposed on the first micro light-emitting element and partially overlaps the first micro light-emitting element in a vertical direction of the substrate. The first connecting line is electrically connected to a first electrode of the first micro light-emitting element and a third semiconductor layer of the repair micro light-emitting element. The second connecting line is electrically connected to a second electrode of the first micro light-emitting element.

Abstract: According to one embodiment, a display device includes an insulating substrate including a first main surface, a first supporting substrate adhered to the first main surface of the insulating substrate, and a second supporting substrate spaced from the first supporting substrate and adhered to the first main surface of the insulating substrate, and the first supporting substrate includes a first side surface opposing the second supporting substrate, the second supporting substrate includes a second side surface opposing the first supporting substrate, the first supporting substrate is formed into a tapered shape which narrows toward the first side surface, and the second supporting substrate is formed into a tapered shape which narrows toward the second side surface.

Abstract: Systems and methods according to one or more embodiments are provided for improved reliability and efficiency of high side power stage output drivers used in switching amplifiers. In one example, a system includes a power device structure comprising an nwell structure formed within a semiconductor p substrate and a pwell structure formed within the nwell structure. The system further includes one or more NMOS electronic power devices formed on the pwell structure and a pwell guardring formed on the pwell structure configured to surround the one or more NMOS electronic power devices. The system further includes an nwell guardring formed on the nwell structure configured to surround the pwell structure and a p+ guardring formed on the nwell structure configured to surround the nwell guardring.

Abstract: A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element having a second principal surface having an electrode arranged thereon, and a photoelectric converter part configured to photoelectrically convert the incident energy line so as to generate a signal charge; a second step of preparing a support substrate, provided with a through hole extending in a thickness direction thereof, having a third principal surface; a third step of aligning the imaging element and the support substrate with each other so that the electrode is exposed out of the through hole while the second and third principal surfaces oppose each other and joining the imaging element and the support substrate to each other; and a fourth step of arranging a conductive ball-shaped member in the through hole and electrically connecting the ball-shaped member to the electrode after the third step.

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

Abstract: A dynamic random access memory (DRAM) cell array using facing bars and a method of fabricating the DRAM cell array are disclosed. A first DRAM cell and a second DRAM cell of each of DRAM cell pairs of a DRAM cell array fabricated using a method of fabricating a DRAM cell array share a facing bar and a bit line plug therebetween. Thus, the overall layout area is greatly reduced by a DRAM cell array fabricated using the method of fabricating the DRAM cell array. Further, in the method of fabricating the DRAM cell array, a storage of each of the DRAM cells of the DRAM cell array is formed as a multi-fin type having a plurality of lateral protrusions, thereby greatly increasing an area of the storage.

Abstract: A method for manufacturing a light emitting element includes: forming a semiconductor structure on a first substrate; providing a second substrate configured to be bonded above a side of the semiconductor structure opposite the first substrate; forming a metal layer above at least one of (i) a side of the semiconductor structure opposite the first substrate, and/or (ii) a side of the second substrate that is to be located closer to the semiconductor structure; bonding the second substrate above the semiconductor structure via a bonding member; removing the first substrate from the semiconductor structure to obtain a bonded body in which the second substrate is bonded above the semiconductor structure; and singulating the bonded body.

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

Abstract: A luminous panel includes a substrate having electric connections and an array of microchips secured to the substrate and connected to the electric connections in order to be driven. Each microchip includes control circuit based on transistors formed in a silicon volume, the circuit being connected to the substrate connections, and a micro-LED secured to the control circuit and connected thereto in order to be controlled.

Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

Abstract: Methods for forming field effect transistors include forming a stack of nanowires of alternating layers of channel material and sacrificial material, with a top layer of the sacrificial material forming a top layer of the stack. A dummy gate is formed over the stack. Channel material and sacrificial material of the stack of nanowires is etched away outside of a region covered by the dummy gate. The sacrificial material is then selectively etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. The dummy gate is etched away with an anisotropic etch. The sacrificial material is etched away to expose the layers of the channel material. A gate stack is formed over and around the layers of the channel material.

Abstract: An avalanche photodiode detector is provided with a substrate including an array of avalanche photodiodes. An optical interface surface of the substrate is arranged for accepting external input radiation. There is provided at least one cross-talk blocking layer of material including apertures positioned to allow external input radiation to reach photodiodes and including material regions positioned for attenuating radiation in the substrate that is produced by photodiodes in the array. Alternatively at least one cross-talk blocking layer of material is disposed on the optical interface surface of the substrate to allow external input radiation to reach photodiodes and attenuate radiation in the substrate that is produced by photodiodes in the array. At least one cross-talk filter layer of material can be disposed in the substrate adjacent to the photodiode structures, including a material that absorbs radiation in the substrate that is produced by photodiodes in the array.

Abstract: A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.

Abstract: A gas sensor device with temperature uniformity is presented herein. In an implementation, a device includes a complementary metal-oxide semiconductor (CMOS) substrate layer, a dielectric layer and a gas sensing layer. The dielectric layer is deposited on the CMOS substrate layer. Furthermore, the dielectric layer includes a temperature sensor and a heating element coupled to a heat transfer layer associated with a set of metal interconnections. The gas sensing layer is deposited on the dielectric layer.