Abstract: A light emitting element includes a semiconductor layer which is in a planar shape of a polygon at least of a pentagon, a second electrode provided on the semiconductor layer, and a first electrode provided on the semiconductor layer and having a first pad portion, a first extension portion that extends from the first pad portion along an imaginary circle to which the first pad portion is tangent on the inside and whose center is at the same location as center of gravity of the polygon shape, and a second extension portion that extends along the imaginary circle from the first pad portion on the opposite side from the first extension portion.

Abstract: There is provided a method of forming a layer, comprising depositing a seed layer on the substrate and depositing a bulk layer on the seed layer. Depositing the seed layer comprises supplying a first precursor comprising metal and halogen atoms to the substrate; and supplying a first reactant to the substrate. Depositing the bulk layer comprises supplying a second precursor comprising metal and halogen atoms to the seed layer and supplying a second reactant to the seed layer.

Abstract: A micro panchromatic QLED array device based on a quantum dot transfer process of deep silicon etching templates. Array-type square table structures pass through a p-type GaN layer and a quantum well active layer and are deep to an n-type GaN layer are disposed on a blue LED epitaxial wafer, wherein micro holes are formed through etching in the structures. Every 2*2 table structures constitute an RGB pixel unit. Among the four micro holes, three of the holes are filled with red light, green light and yellow light quantum dots respectively, and one of the holes emits blue light/is filled with a blue light quantum dot. Micro holes in a silicon wafer are formed through etching with a deep silicon etching technology; the micro holes in the silicon wafer are aligned with quantum dot filling areas on a micro-LED.

Abstract: A lighting device includes a substrate having a light emitting area and a non-light emitting area surrounding the light emitting area, a light emitting part in the light emitting area, a first inorganic layer on the light emitting part and the non-light emitting area, a first organic layer on the first inorganic layer overlapping the light emitting part, a second inorganic layer on the first organic layer, a protruding part on the first inorganic layer of the non-light emitting area, and a cover layer on the protruding part.

Abstract: A method includes forming a dielectric layer over a conductive feature, forming an opening in the dielectric layer, and plating a metallic material to form a redistribution line electrically coupled to the conductive feature. The redistribution line includes a via in the opening, and a metal trace. The metal trace includes a first portion directly over the via, and a second portion misaligned with the via. A first top surface of the first portion is substantially coplanar with a second top surface of the second portion of the metal trace.

Abstract: A display apparatus includes thin-film transistors respectively provided for pixels arranged in a matrix form, one or more driving circuits provided at a side of one end of the display panel, a plurality of signal lines to each connect more than one of the plurality of thin-film transistors arranged in one line in the matrix form to the driving circuit, a plurality of spare lines formed to be connectable to any of the plurality of signal lines in an outer area of a display panel, and arranged separated from one another in an opposing region in the outer area, the opposing region being opposed to the driving circuits across the display area, and a metal pattern overlapping a first spare line and a second spare line with an insulating layer therebetween, so as to be connectable to the first spare line arranged in a first region and the second spare line arranged in a second region.

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.

Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.

Abstract: A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.

Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

Abstract: A-light-emitting device which realizes a high aperture ratio and in which the quality of image is little affected by the variation in the characteristics of TFTs. The channel length of the driving TFTs is selected to be very larger than the channel width of the driving TFTs to improve current characteristics in the saturated region, and a high VGS is applied to the driving TFTs to obtain a desired drain current. Therefore, the drain currents of the driving TFTs are little affected by the variation in the threshold voltage. In laying out the pixels, further, wiring is arranged under the partitioning wall and the driving TFTs are arranged under the wiring in order to avoid a decrease in the aperture ratio despite of an increase in the size of the driving TFT.

Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.

Abstract: A manufacturing method of a semiconductor chip is provided. The method includes: forming a first metal pattern over a substrate and within a chip region and a scribe line region of the substrate, wherein the chip region is surrounded by the scribe line region; forming a metal material layer on the first metal pattern; patterning the metal material layer to remove substantially all portions of the metal material layer within the scribe line region and a portion of the metal material layer within the chip region, so as to form a second metal pattern within the chip region; forming a third metal pattern, wherein the second metal pattern within the chip region is covered by the third metal pattern, and the third metal pattern is located over the first metal pattern within the scribe line region; and performing singulation along the scribe line region, to form the semiconductor chip.

Abstract: A method (of forming an integrated circuit) includes: forming a first diode on a first substrate of two or more stacked substrates, the first substrate having a first predetermined doping type; forming a second diode on a second substrate of the two or more stacked substrates, the second substrate being formed on the first substrate, and the second substrate having the first predetermined doping type; and forming conductive paths electrically connecting the first diode 3A and the second diode between a circuit and a first common ground rail, the first diode and the second diode being connected in parallel and having opposite polarities.

Abstract: There is provided a method of manufacturing an imaging device including a plurality of imaging elements in an imaging area, where each imaging element includes a photoelectric conversion unit in a substrate and a wire grid polarizer arranged at a light-incident side of the photoelectric conversion unit. The method generally includes forming the wire grid polarizer that includes a plurality of stacked strip-shaped portions, where each of the plurality of stacked strip-shaped portions includes a portion of a light-reflecting layer and a portion of a light-absorbing layer. The light-reflecting layer may include a first electrical conducting material that is electrically connected to at least one of the substrate or the photoelectric conversion unit. The light-absorbing layer may include a second electrical conducting material, where at least a portion of the light-absorbing layer is in contact with the light-reflecting layer.

Abstract: A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.

Abstract: On the front side of an n-type semiconductor substrate, p-type regions are two-dimensionally arranged in an array. A high-concentration n-type region and a p-type region are disposed between the p-type regions adjacent each other. The high-concentration n-type region is formed by diffusing an n-type impurity from the front side of the substrate so as to surround the p-type region as seen from the front side. The p-type region is formed by diffusing a p-type impurity from the front side of the substrate so as to surround the p-type region and high-concentration n-type region as seen from the front side. Formed on the front side of the n-type semiconductor substrate are an electrode electrically connected to the p-type region and an electrode electrically connected to the high-concentration n-type region and the p-type region.

Abstract: A method for manufacturing a semiconductor memory device includes forming a bottom electrode on a bottom contact layer, and forming a dielectric layer covering sides of the bottom electrode. In the method, a switching element layer is deposited on the dielectric layer and the bottom electrode, a top electrode layer is deposited on the switching element layer, and a hardmask layer is deposited on the top electrode layer. The switching element, top electrode and hardmask layers are patterned into a pillar on the bottom electrode. The method further includes forming a spacer layer on the dielectric layer on sides of the pillar, and forming a metal layer on the dielectric layer adjacent the spacer layer and around the pillar.

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.