Patents Examined by Hsin-Yi Hsieh
  • Patent number: 11735695
    Abstract: Described are light emitting diode (LED) devices comprising a plurality of mesas defining pixels, each of the mesas comprising semiconductor layers, an N-contact material in a space between each of the plurality of mesas, a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal. A current spreading layer is on the P-type layer, the current spreading layer having a first portion and a second portion; a hard mask layer above the second portion of the current spreading layer, the hard mask layer comprising sidewalls defining a hard mask opening; a liner layer conformally-deposited in the hard mask opening above the first portion of the current spreading layer and on the sidewalls of the hard mask layer; a P-metal material plug on the liner layer; a passivation layer on the hard mask layer; and an under bump metallization layer on the passivation layer.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 22, 2023
    Assignee: Lumileds LLC
    Inventors: Erik William Young, Rajat Sharma, Dennis Scott
  • Patent number: 11735686
    Abstract: A method for manufacturing a light-emitting element includes dividing a semiconductor structure into a plurality of light-emitting portions by removing a portion of the semiconductor structure so as to form an exposed region, a first surface being exposed from under the semiconductor structure in the exposed region; etching protrusions formed in the exposed region; bonding a light-transmitting body to a second surface so as to form a bonded body; forming a plurality of modified regions along the exposed region inside the substrate by irradiating a laser beam on the exposed region from the first surface side; removing a portion of the light-transmitting body that overlaps the plurality of modified regions in a plan view; and singulating the bonded body along the modified regions.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 22, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Yoshiki Inoue, Shun Kitahama, Yoshiyuki Aihara, Yoshiki Matsushita, Keisuke Higashitani
  • Patent number: 11728389
    Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: August 15, 2023
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Jan Ropohl
  • Patent number: 11705537
    Abstract: Disclosed are a display device and a manufacturing method thereof. The display device includes a plurality of pixels, a light emitting device provided in each of the plurality of pixels, the light emitting device having a first surface and a second surface, which are opposite to each other, a first electrode electrically connected to the first surface of the light emitting device, a second electrode electrically connected to the second surface of the light emitting device, and a metal oxide pattern interposed between the second surface of the light emitting device and the second electrode. The metal oxide pattern is provided to cover a portion of the second surface and to expose a remaining portion of the second surface. The second electrode is electrically connected to the exposed remaining portion of the second surface, and the metal oxide pattern includes single-crystalline or polycrystalline alumina.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: July 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO.,. LTD.
    Inventors: Euijoon Yoon, Jehong Oh, Jungel Ryu, Seungmin Lee, Jongmyeong Kim
  • Patent number: 11658235
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first region, and a first insulating layer. The first electrode includes a first electrode portion. The first region contains Ga and N. The first region includes a first subregion, a second subregion, and a third subregion. The first subregion and the third subregion contain at least one first element selected from the group consisting of Ar, B, P, N, and Fe. The first subregion is located between the first electrode portion and the second subregion in a first direction. The second subregion does not contain the first element, or concentration of the first element in the second subregion is lower than concentration of the first element in the first subregion and lower than concentration of the first element in the third subregion. The first insulating layer is provided between the first electrode and the first region.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: May 23, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Miki Yumoto, Hiroshi Ono
  • Patent number: 11652122
    Abstract: There is provided a method of manufacturing an imaging device including a plurality of imaging elements in an imaging area, where each imaging element includes a photoelectric conversion unit in a substrate and a wire grid polarizer arranged at a light-incident side of the photoelectric conversion unit. The method generally includes forming the wire grid polarizer that includes a plurality of stacked strip-shaped portions, where each of the plurality of stacked strip-shaped portions includes a portion of a light-reflecting layer and a portion of a light-absorbing layer. The light-reflecting layer may include a first electrical conducting material that is electrically connected to at least one of the substrate or the photoelectric conversion unit. The light-absorbing layer may include a second electrical conducting material, where at least a portion of the light-absorbing layer is in contact with the light-reflecting layer.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: May 16, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Tomohiro Yamazaki, Yasushi Maruyama
  • Patent number: 11626533
    Abstract: There is provided a light emitting device including: a substrate; a laminated structure provided on the substrate and having a plurality of first columnar portions and a plurality of second columnar portions; and a first electrode and a second electrode, in which the first columnar portion includes a first semiconductor layer, a second semiconductor layer having a conductivity type different from the first semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, light generated in the light emitting layer propagates through the plurality of first columnar portions and the plurality of second columnar portions, a height of the second columnar portion is equal to or larger than a sum of a thickness of the first semiconductor layer and a thickness of the light emitting layer, and is lower than a height of the first columnar portion, the first semiconductor layer is provided between the substrate and the light emitting layer, the first elec
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 11, 2023
    Inventors: Shunsuke Ishizawa, Katsumi Kishino
  • Patent number: 11616164
    Abstract: A method for producing a nitride compound semiconductor component is disclosed. In an embodiment the method includes providing a growth substrate, growing a nucleation layer of an aluminum-containing nitride compound semiconductor onto the growth substrate, growing a tension layer structure for generating a compressive stress, wherein the tension layer structure comprises at least a first GaN semiconductor layer and a second GaN semiconductor layer, and wherein an Al(Ga)N interlayer for generating the compressive stress is disposed between the first GaN semiconductor layer and the second GaN semiconductor layer and growing a functional semiconductor layer sequence of the nitride compound semiconductor component onto the tension layer structure, wherein a growth of the second GaN semiconductor layer is preceded by a growth of a first 3D AlGaN layer on the Al(Ga)N interlayer in such a way that it has nonplanar structures.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: March 28, 2023
    Assignee: OSRAM OLED GMBH
    Inventors: Philipp Drechsel, Werner Bergbauer, Thomas Lehnhardt, Jürgen Off, Joachim Hertkorn
  • Patent number: 11610868
    Abstract: The invention relates to various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 21, 2023
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Peter Brick, Jean-Jacques Drolet, Hubert Halbritter, Laura Kreiner, Thomas Schwarz, Julia Stolz
  • Patent number: 11581197
    Abstract: This method for producing a semiconductor device comprises: a first step wherein a plurality of semiconductor chips are affixed onto a supporting substrate such that circuit surfaces of the semiconductor chips face the supporting substrate; a second step wherein a plurality of sealed layers are formed at intervals by applying the sealing resin onto the semiconductor chips by three-dimensional modeling method, each sealed layer containing one or more semiconductor chips embedded in a sealing resin; a third step wherein the sealed layers are cured or solidified; and a fourth step wherein sealed bodies are obtained by separating the cured or solidified sealed layers from the supporting substrate.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: February 14, 2023
    Assignee: MITSUI CHEMICALS, INC.
    Inventors: Jun Kamada, Kaichiro Haruta, Yasuhisa Kayaba, Kazuo Kohmura, Yoichi Kodama
  • Patent number: 11574944
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: February 7, 2023
    Inventors: Motomu Kurata, Ryota Hodo, Yuta Iida
  • Patent number: 11557702
    Abstract: A method for manufacturing a light-emitting device includes providing a transparent member having a protrusion formed at an upper surface of the transparent member. A first resin portion is placed on the protrusion in which the first resin portion has a solid form and is made from a first resin material of which the viscosity decreases when heated. A light-emitting element is placed on the first resin portion, the light-emitting element is caused to be self-aligned with respect to the protrusion by reducing a viscosity of the first resin portion by heating to a first temperature. The first resin portion is solidified by cooling.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: January 17, 2023
    Assignee: NICHIA CORPORATION
    Inventor: Toru Hashimoto
  • Patent number: 11538767
    Abstract: An integrated circuit includes a lead frame, a first die, and a second die. The first die is bonded to and electrically connected to the lead frame. The second die is electrically connected to and spaced apart from the first die.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: December 27, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Paul Merle Emerson, Kurt Peter Wachtler
  • Patent number: 11538962
    Abstract: A light-emitting element includes: a first n-type nitride semiconductor layer; a first light-emitting layer located on the first n-type nitride semiconductor layer; a p-type GaN layer located on the first light-emitting layer; an n-type GaN layer located on the p-type GaN layer and doped with an n-type impurity at an impurity concentration higher than that of the first n-type nitride semiconductor layer; a non-doped GaN layer located between the p-type GaN layer and the n-type GaN layer, a thickness of the non-doped GaN layer being not more than a width of a depletion layer formed by the n-type and p-type GaN layers; a second n-type nitride semiconductor layer located on the n-type GaN layer and doped with an n-type impurity; a second light-emitting layer located on the second n-type nitride semiconductor layer; and a p-type nitride semiconductor layer located on the second light-emitting layer and doped with a p-type impurity.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: December 27, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Seiichi Hayashi
  • Patent number: 11527674
    Abstract: A method includes: bonding a surface of a first wafer on a side having a semiconductor layer to a surface of a second wafer on a side having a first electrode to electrically connect the semiconductor layer and the first electrode; etching a silicon substrate such that a first portion of the silicon substrate remains in a region overlapping with the first electrode in a plan view; etching the semiconductor layer using the first portion as a mask such that a portion of the semiconductor layer between the first portion and the first electrode remains as at least one light-emitting portion; forming a resin layer to cover a lateral surface of the first portion and a lateral surface of the light-emitting portion with the resin layer; removing the first portion to expose the light-emitting portion; and forming a light-transmissive electrically conductive film on or above the light-emitting portion.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: December 13, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Hirofumi Nishiyama
  • Patent number: 11522109
    Abstract: A light emitting package structure and a method of manufacturing the light emitting package structure are provided. The method includes: a preparation process: mounting a light emitting unit on a substrate; a dispensing process: coating a sealant on a first joint area of the substrate; a cover-enclosing process: disposing a cover element having a second joint area on the substrate, the first joint area and the second joint area joined to each other by the sealant; a vacuum process: reducing an ambient pressure to a first pressure lower than the original ambient pressure; a pressure-adjusting process: adjusting the ambient pressure around the package structure to a second pressure higher than the first pressure; and a curing process: curing the sealant.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 6, 2022
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Wei-Te Cheng, Kuo-Ming Chiu, Kai-Chieh Liang, Jie-Ting Tsai
  • Patent number: 11511467
    Abstract: The present invention relates to the field of automotive lamps, particularly a method for manufacturing a light emitting device (10) for use in automotive lamps. The method comprises: providing a base substrate (11) with a LED die (12) and one or more electrical components (13) attached thereon into a first mold; melting and injecting an optical transparent material over the LED die (12) to form an optical structure (14); removing the base substrate (11) from the first mold once the optical transparent material is partially solidified; providing the base substrate (11) into a second mold different from the first mold; and melting and injecting a thermally conductive material into the second mold while the optical transparent material is not fully solidified, such that an intimate connection is formed between the thermally conductive material and the optical transparent material. The present invention further discloses the light emitting device (10) per se.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: November 29, 2022
    Assignee: Lumileds LLC
    Inventors: Nan Chen, Paul Scott Martin, Chao Ding, Luke Cheng
  • Patent number: 11495606
    Abstract: A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Po Chang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Wei-Yang Lee, Tzu-Hsiang Hsu
  • Patent number: 11495494
    Abstract: An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun Lee, Chen-Ming Lee, Fu-Kai Yang, Yi-Jyun Huang, Sheng-Hsiung Wang, Mei-Yun Wang
  • Patent number: 11495652
    Abstract: An organic light emitting diode display device includes a substrate, a driving transistor, a switching transistor, a first light absorbing layer, an organic insulating layer, and a sub-pixel structure. The substrate includes a first region and a second region. The driving transistor is disposed in the first region on the substrate. The switching transistor is disposed in the second region on the substrate, and includes a metal-oxide-based semiconductor. The first light absorbing layer is disposed on the driving and switching transistors. The organic insulating layer is disposed directly on the first light absorbing layer. The sub-pixel structure is disposed on the organic insulating layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 8, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Junhee Lee, Dongwon Kim, Deokhoi Kim, Injun Bae, Hyemin Lee, Jihee Kim