Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The integrated circuit package includes first and second active dies. Each of the first and second active dies includes a top contact disposed on the top surface of the die and a bottom contact disposed on a bottom surface of the die. The package further includes a via die having first and second vias that each extends between a top contact disposed on a top surface of the via die and a bottom contact disposed on a bottom surface of the via die, where the bottom contact of the first active die is electrically connected to the bottom contact of the first via of the via die and the bottom contact of the second active die is electrically connected to the bottom contact of the second via of the via die.

Abstract: An organic light emitting diode display is disclosed. The organic light emitting diode display includes: a substrate, an organic light emitting diode positioned on the substrate, a metal layer positioned on the substrate with the organic light emitting diode interposed therebetween, and a resin layer positioned on the metal layer and configured to reinforce a strength of the metal layer.

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

Abstract: A lighting apparatus using an organic light emitting diode that has an emission area and a non-emission area, the light emitting apparatus comprises a first electrode; an organic layer disposed on the first electrode; a second electrode disposed on the organic layer; and an insulating layer disposed in the non-emission area, wherein the first electrode disposed in the emission area includes at least one metal layer and at least one dielectric layer, and wherein the first electrode disposed in the non-emission area includes at least one dielectric layer.

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.

Abstract: A semiconductor light emitting element includes: an n-type semiconductor layer provided on a substrate; an active layer provided in a first region of the n-type semiconductor layer and made of an AlGaN-based semiconductor material; a p-type semiconductor layer provided on the active layer; a first protective layer provided on the p-type semiconductor layer and made of silicon oxide (SiO2) or silicon oxynitride (SiON); a second protective layer provided to cover a top of the first protective layer, a second region on the n-type semiconductor layer different from the first region, and a lateral surface of the active layer and made of aluminum oxide (Al2O3), aluminum oxynitride (AlON), or aluminum nitride (AlN); a p-side electrode provided contiguously on the p-type semiconductor layer; and an n-side electrode provided contiguously on the n-type semiconductor layer.

Abstract: An integrated circuit includes two or more substrates stacked one over another and a first set of electrical components on one or more of the two or more substrates. The two or more substrates include a first substrate having a first predetermined doping type and a second substrate having the first predetermined doping type. The first set of electrical components is configured to form a first circuit. The integrated circuit further includes a first ground reference rail electrically connected to the first circuit, a first common ground reference rail, and a first ESD conduction element electrically connected between the first ground reference rail and the first common ground reference rail. The first ESD conduction element includes a first diode on the first substrate and a second diode on the second substrate. The first diode and the second diode are electrically connected in parallel and have opposite polarities.

Abstract: A method is described for low temperature curing of silicone structures, including the steps of providing patterning photoresist structures on a substrate. The photoresist structures define at least one open region that can be at least partially filled with a condensation cure silicone system. Vapor phase catalyst deposition is used to accelerate the cure of the condensation cure silicone, and the photoresist structure is removed to leave free standing or layered silicone structures. Phosphor containing silicone structures that are coatable with a reflective metal or other material are enabled by the method.

Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

Abstract: A layered metal oxide field effect material forms a heterojunction from metal oxides with different band gaps, and defines a band gap difference (?E)?1 eV. Band bending is generated at the interface of the heterojunction, such that a potential barrier is formed on the side with the larger band gap and a triangular potential well is formed on the side with the smaller band gap, and under the induction of a gate electric field, a polarized charge is generated at the interface of the heterojunction, and a large number of carriers are accumulated. Therefore, the present layered metal oxide field effect material has high carrier mobility higher than 103 cm2/V·s, and overcomes the problem that the carrier mobility of a conventional metal oxide field effect material is low, it is required to fabricate the metal oxide field effect material into a crystal phase structure with a relatively high cost, and even that a substrate thereof with a crystal phase structure is required.

Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: A semiconductor device includes a tube-like structure comprising a plurality of dielectric layers and conductor layers that are disposed on top of one another; a conductor tip integrally formed with a cap conductor layer that is disposed on a top surface of the tube-like structure, wherein the conductor tip extends to a central hole of the tube-like structure; and at least one photodetector formed within a bottom portion of the tube-like structure.

Abstract: A manufacturing method of TFT substrate and a TFT substrate are provided. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.

Abstract: A capacitor structure includes a substrate having thereon a storage node contact, a cylinder-shaped bottom electrode disposed on the storage node contact, a supporting structure horizontally supporting a sidewall of the cylinder-shaped bottom electrode, a capacitor dielectric layer conformally covering the cylinder-shaped bottom electrode and the supporting structure, and a top electrode covering the capacitor dielectric layer. The supporting structure has a top surface that is higher than that of the cylinder-shaped bottom electrode. The top surface of the supporting structure has a V-shaped sectional profile.

Abstract: Provided are a group III nitride semiconductor light emitting element and a method of manufacturing the same. A group III nitride semiconductor light emitting element of the present disclosure comprises in this order, in a substrate, an n-type semiconductor layer, a light emitting layer, a p-type electron blocking layer, a p-type contact layer made of AlxGa1-xN, and a p-side reflection electrode, wherein a center emission wavelength of light emitted from the light emitting layer is 270 nm or greater and 330 nm or smaller, the p-type contact layer is in contact with the p-side reflection electrode, and has a thickness of 20 nm or greater and 80 nm or smaller, and the Al composition ratio x of the p-type contact layer satisfies the following Formula: 2.09?0.006×?p?x?2.25?0.006×?p where ?p is the center emission wavelength in nanometer.

Abstract: The array of gallium-nitride (GaN) nanocolumns have quantum wells in a polar c-plane or in a semi-polar plane to emit light directed to ends of the nanocolumns and an interstitial filler material with light emitted in the nanocolumns being guided to exit from an end of the nanocolumns.

Abstract: An integrated circuit is provided with a memory cell array comprising poly lines, semiconductor lines extending in a first direction and transistor devices, wherein gates of the transistor device are formed in portions of the poly lines and channels of the transistor devices are formed in the semiconductor lines and wherein at least one portion of at least one of the poly lines runs across at least one of the semiconductor lines in a second direction inclined to a direction perpendicular to the first direction at an inclination angle of more than, for example, 5° or 10°, as measured from the direction perpendicular to first direction.

Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.

Abstract: A method of manufacturing a light emitting device is provided. The method includes providing a lead frame including a plurality of light emitting devices each including: a light emitting element; a resin molded body including a lead electrode on which the light emitting element is mounted, and a light-shielding member which supports the lead electrode and has a recess accommodating the light emitting element; and a light-transmissive member disposed in the recess. The method further includes: providing a mask including a plurality of through holes, and overlaying the mask on the lead frame so that the resin molded body and the light-transmissive member are exposed at the through holes; and perforating abrasive blasting by blowing a particulate material on a surface of the resin molded body and a surface of the light-transmissive member.