Abstract: The light emitting device includes a light emitting element having an electrode-formed surface on which electrode posts are formed; a covering member covering the electrode-formed surface and lateral surfaces of the light emitting element while forming an exposure portion of each of the electrode posts which are exposed from the covering member; a pair of electrode layers provided on a surface of the covering member and electrically connected to the exposed portions of the electrode posts; and a pair of electrode terminals which are respectively electrically connected to the electrode layers, having a surface area larger than a surface area of the electrode posts, and having an outer edge positioned at an end portion of the covering member; and an insulating member provided between the pair of the electrode terminals while being in contact with lateral surfaces of the pair of electrode terminals.

Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.

Abstract: A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a gate electrode formed on the main surface of the semiconductor substrate, a side-wall oxide film formed on a side wall of the gate electrode, a first insulating layer formed on the gate electrode and containing silicon nitride, and a second insulating layer formed between the gate electrode and the first insulating layer and containing silicon oxide.

Abstract: An optoelectronic component that emits electromagnetic radiation from a radiation exit surface of the optoelectronic component includes a radiation-emitting semiconductor chip that produces electromagnetic radiation, and a marker element applied to the radiation exit surface of the optoelectronic component, the marker element including a dye substance that can be removed from the radiation exit surface using a solvent and/or is permeable to the electromagnetic radiation of the optoelectronic component, wherein the dye substance includes a resin into which fluorescent particles are introduced that convert electromagnetic radiation of a first wavelength range into electromagnetic radiation of a second wavelength range, the first wavelength range and the second wavelength range being within the ultraviolet spectral range.

Abstract: An embodiment of the present invention provides a micro light emitting diode (LED) array and its manufacturing method. The micro-LED includes a substrate, an epitaxial layer formed on the substrate, and a conversion film formed on the epitaxial layer. Pixels can be defined through lithography, and the pixel size can be very small. This method is characterized in that a mass transfer is not required.

Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: An image sensing device capable of minimizing reflection of light incident upon a metal layer is disclosed. The image sensing device includes a semiconductor substrate in which at least one groove is formed, a reflection prevention layer formed over the semiconductor substrate in a manner that the at least one groove is buried by the reflection prevention layer, and a metal layer formed over the reflection prevention layer, and provided with at least one through-hole corresponding to the at least one groove.

Abstract: The array of gallium-nitride (GaN) nanocolumns have quantum wells in a polar c-plane or in a semi-polar plane to emit light directed to ends of the nanocolumns and an interstitial filler material with light emitted in the nanocolumns being guided to exit from an end of the nanocolumns.

Abstract: A structure manufacturing method including: preparing a treatment object that includes an etching target having a surface to be etched comprising a conductive group III nitride and a region to be etched, a conductive member in contact with at least a portion of a surface of a conductive region of the etching target that is electrically connected to the region to be etched, and a mask formed on the surface to be etched and comprising a non-conductive material; and etching the group III nitride by immersing the treatment object in an alkaline or acidic etching solution containing peroxodisulfate ions as an oxidizing agent that accepts electrons, and irradiating the surface to be etched with light through the etching solution, wherein an edge that defines the region to be etched is constituted by an edge of the mask without including an edge of the conductive member.

Abstract: The nitride-based semiconductor device includes a carrier traveling layer 1 composed of non-doped AlXGa1-XN (0?X<1); a barrier layer 2 formed on the carrier traveling layer 1 and composed of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the carrier traveling layer 1; a threshold voltage control layer 3 formed on the barrier layer 2 and composed of a non-doped semiconductor having a lattice constant equal to that of the carrier traveling layer 1; and a carrier inducing layer 4 formed on the threshold voltage control layer 3 and composed of a non-doped or n-type semiconductor having a lattice constant smaller than that of the carrier traveling layer 1. The nitride-based semiconductor device further includes a gate electrode 5 formed in a recess structure, a source electrode 6 and a drain electrode 7.

Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.

Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having first and second sides; forming at least one doping region at the first side; forming a first metallization structure at the first side on and in contact with the at least one doping region; and subsequently forming a second metallization structure at the second side, the second metallization structure forming at least one silicide interface region with the semiconductor substrate and at least one non-silicide interface region with the semiconductor substrate.

Abstract: A method of making a semiconductor device, comprising: forming a plurality of semiconductor seeds of a first III-nitride material through a mask provided over a substrate; growing a second III-nitride semiconductor material; planarizing the grown second semiconductor material to form a plurality of discrete base elements having a substantially planar upper surface. Preferably the step of planarizing involves performing atomic distribution of III type atoms of the grown second semiconductor material under heating to form the planar upper surface, and without supply of III type atoms is carried out during the step of planarization.

Abstract: A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer.

Abstract: Apparatuses and methods for internal heat spreading for packaged semiconductor die are disclosed herein. An example apparatus may include a plurality of die in a stack, a bottom die supporting the plurality of die, a barrier and a heat spreader. A portion of the bottom die may extend beyond the plurality of die and a top surface of the bottom die extending beyond the plurality of die may be exposed. The barrier may be disposed alongside the plurality of die and the bottom die, and the heat spreader may be disposed over the exposed top surface of the bottom die and alongside the plurality of die.

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.

Abstract: A method of producing an optoelectronic component includes providing an opto-electronic semiconductor chip including a layer sequence arranged on a substrate, wherein the layer sequence includes a contact side including two electrical contact locations, the contact side facing away from the substrate; arranging the optoelectronic semiconductor chip on an auxiliary carrier such that the contact side faces away from the auxiliary carrier; arranging a molding material above the auxiliary carrier such that a housing is formed that at least partly encloses the optoelectronic semiconductor chip, wherein the contact side is covered by the molding material; and detaching the housing from the auxiliary carrier.

Abstract: Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.