Abstract: A phosphor material according to an embodiment of the present disclosure contains a major component represented by the formula A2-v-w-x-yBvLnwEuxSmyM2-zDzO8, where A is one or more elements selected from the group consisting of alkaline-earth metal elements; B is one or more elements selected from the group consisting of alkali metal elements; Ln is one or more elements selected from the group consisting of rare-earth elements other than Eu and Sm; M is one or more elements selected from the group consisting of W and Mo; D is one or more elements selected from the group consisting of Nb and Ta; and v, w, x, y, and z satisfy the inequalities 0?v?0.5, 0.15?x+y?0.7, 0?y?0.05, and 0<z?1.7 and the equation w+x+y=v+z.

Abstract: A method for forming a photo diode is provided. The method includes: forming a first pair of electrodes and a second pair of electrodes over a substrate by using a conductive layer; forming a dielectric layer over the substrate; patterning the dielectric layer over the substrate; forming a photo conversion layer over the substrate; and forming a color filter layer over the photo conversion layer, wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a first pixel from a second portion of the color filer layer corresponding to a second pixel, and a refractive index of the dielectric layer is lower than a refractive index of the color filter layer, wherein the first pair of electrodes corresponds to the first pixel and the second pair of electrodes corresponds to the second pixel.

Abstract: A method for fabricating a semiconductor device in which a lifetime control region can be formed within a predetermined range with high positioning accuracy is provided. In a semiconductor device, an IGBT element region and a diode element region may be formed in one semiconductor substrate. The IGBT element region may include a second conductivity type drift layer and a first conductivity type body layer. The diode element region may include a second conductivity type drift layer and a first conductivity type anode layer. A concentration of heavy metal included in the drift layer of the diode element region may be set higher than a concentration of the heavy metal included in the drift layer of the IGBT element region.

Abstract: An ultraviolet sensor having a p-type semiconductor layer containing, as its main constituent, a solid solution of NiO and ZnO, and an n-type semiconductor layer containing ZnO as its main constituent, which is joined to the p-type semiconductor layer such that a portion of the p-type semiconductor layer is exposed. An internal electrode is buried in the p-type semiconductor layer and opposed to the n-type semiconductor layer. Both ends of the internal electrode are exposed at both end surfaces of the p-type semiconductor layer, and first and second high-resistance layers composed of insulating materials cover one end of the internal electrode. The second high-resistance layer is obtained by diffusion of the insulating material from the first high-resistance layer into the p-type semiconductor layer. A first external electrode is connected to the other end of the internal electrode, and a second external electrode is connected to the n-type semiconductor layer.

Abstract: The disclosure is directed to a semiconductor wafer, integrated circuit product, and method of making same, having multiple non-singulated chips separated by scribe lines, comprising a plurality of seal rings, each seal ring surrounding a corresponding chip and disposed between the corresponding chip and adjacent scribe lines. Well resistors are disposed below the seal rings and probe pads disposed in the scribe lines. In particular, at least one of the probe pads is coupled by at least one of the well resistors to at least one of the chips.

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract: According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip.

Abstract: A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen.

Abstract: A chip-housing module is provided, the chip-housing module including a carrier configured to carry one or more chips; the carrier including a first plurality of openings, wherein each opening of the first plurality of openings is separated by a first pre-determined distance, and is configured to receive a chip connection for providing a voltage lying within a first range of voltage values to a chip; the carrier including a second plurality of openings, wherein each opening of the second plurality of openings is separated by a second pre-determined distance, and is configured to receive a chip connection for providing a voltage lying within a second range of voltage values to a chip; and wherein a pair of openings consisting of one opening of the first plurality of openings and one opening of the second plurality of openings is separated by a distance different from at least one of the first pre-determined distance and the second pre-determined distance.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).

Abstract: An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within encapsulation. The lead frame includes a first conductor having a first conductive loop disposed substantially within the encapsulation. The lead frame also includes a second conductor that is galvanically isolated from the first conductor. The second conductor includes a second conductive loop that is substantially disposed within the encapsulation proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductors.

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.

Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.

Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

Abstract: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.

Abstract: A semiconductor device has a carrier with a die attach area. Recesses are formed partially through the carrier outside the die attach area. A first conductive layer is conformally applied over a surface of the carrier and into the recesses. A semiconductor die is mounted to the die attach area of the carrier. An encapsulant is deposited over the carrier and semiconductor die. The encapsulant extends into the recesses over the first conductive layer to form encapsulant bumps. The carrier is removed to expose the first conductive layer over the encapsulant bumps. A first insulating layer is formed over the semiconductor die with openings to expose contact pads of the semiconductor die. A second conductive layer is formed between the first conductive layer and the contact pads on the semiconductor die. A second insulating layer is formed over the second conductive layer and semiconductor die.

Abstract: In general, according to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region and a peripheral region. The memory cell region includes first element isolation regions, first semiconductor regions, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. The first element isolation regions separate a semiconductor layer and include a first insulating film. The first semiconductor regions are separated by the first element isolation regions. The peripheral region includes a second element isolation region a second insulating film. Each of the first element isolation regions includes a first and a second portion. A step is present between the first and the second portion. At least part of a side surface and a lower end of the second element isolation region are surrounded by the semiconductor layer.

Abstract: A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts.

Abstract: A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Abstract: A lighting module may include a lighting band with a band-shaped flexible substrate, wherein at least one semiconductor light source is applied to a top side of the substrate, wherein the lighting module is faced with a protective layer such that at least one emission area of the at least one semiconductor light source is exposed thereby.