Abstract: A package system includes a first substrate; and a second substrate electrically coupled with the first substrate. The package system further includes a semiconductor material between the first substrate and the second substrate. The semiconductor material includes a pad, and at least one guard ring surrounding the pad and spaced from the pad. The package system further includes a metallic material bonded to the semiconductor material, wherein the metallic material at least partially fills at least one opening in at least one of the first substrate or the second substrate.

Abstract: Some demonstrative embodiments include devices and/or methods of Back Side Illumination (BSI) Complementary Metal-Oxide-Semiconductor (CMOS) pixel array. For example, a BSI CMOS pixel array may include a plurality of pixels, a pixel of the plurality of pixels may include one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of the one or more well regions comprising an N-Well (NW) region or a P-well (PW) region; a photodiode; an epitaxial (epi) layer comprising an absorption area and a collection area, the absorption area to absorb incoming photons and to generate electrons responsive to absorbed photons, and the collection area connecting the absorption area to the photodiode to provide the electrons from the absorption area to the photodiode; and a barrier layer separating the absorption area from the one or more well regions.

Abstract: A method includes providing a substrate having a metal-oxide-semiconductor (MOS) region. The MOS region includes first gate, source, and drain regions for a first device, and second gate, source, and drain regions for a second device. The first gate region has a first length. The second gate region has a second length different from the first length. The method further includes forming first and second fins in the first and second gate regions, forming first and second semiconductor layer stacks over the first and second fins, and performing a thermal oxidation process to the first and second semiconductor layer stacks, thereby forming first and second nanowire sets in the first and second gate regions respectively. The first and second nanowire sets are wrapped by respective semiconductor oxide layers. The first nanowire set has a first diameter. The second nanowire set has a second diameter different from the first diameter.

Abstract: A semiconductor device includes a substrate, a first trough structure and a second trough structure. The first trough structure which is in the substrate includes a first conductive layer, a first doping layer and a first insulation layer, which is placed between the first conductive layer and the first doping layer. The second trough structure which is in the substrate and separated from the first trough structure by a separation part of the substrate includes a second conductive layer and a second insulation layer. A first contact connects the first doping layer, a second contact connects the separation part, and a third contact connects the second conductive layer. The separation part forms a resistor, coupled between the first contact and the second contact, and the substrate, the second insulation layer and the second conductive layer together form a capacitor, coupled between the second contact and the third contact.

Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).

Abstract: An encapsulation structure comprising at least: a hermetically sealed cavity in which a micro-device is encapsulated, a substrate of which one face delimits one side of the cavity, at least two trenches formed through said face of the substrate, the interior volumes of each of the trenches communicating together, first portions of getter material covering at least in part side walls of the trenches without entirely filling the trenches, and completely covering the trenches at said face of the substrate, an opening formed through one of the first portions of getter material or through the substrate and making the interior volumes of the trenches communicate with an interior volume of the cavity.

Abstract: A semiconductor device includes, on one semiconductor substrate: a first element isolation region having a first width, wherein a liner oxide film, a liner nitride film and a silicon dioxide film are provided in succession from an outer peripheral side of an upper surface of the first element isolation region; and a second element isolation region having a second width that is larger than the first width, wherein a liner oxide film and a silicon dioxide film are provided in succession from an outer peripheral side of an upper surface of the second element isolation region.

Abstract: An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within the encapsulation. The lead frame includes a first conductor forming a first conductive loop. A second conductor is galvanically isolated from the first conductor. The second conductor forms a second conductive loop proximate to and magnetically coupled to the first conductive loop to provide a magnetic communication link between the first and second conductors. A signal that is transmitted from a transmit circuit coupled to the first conductor is coupled to be received through the magnetic communication link by a receive circuit coupled to the second conductor.

Abstract: To provide a light emitting device that can suppress the increase in pits and projections caused by the thermal history of the reflective film on the surface of the reflective film used in the light emitting device, the light emitting device includes: a light emitting element; and a reflective film for reflecting light from the light emitting element, in which the reflective film contains silver as a principal component, and nanoparticles of an oxide.

Abstract: An object of the present invention is to provide a method of manufacturing a flip-chip type semiconductor device with a simplified process, in which various types of information are supplied in a visually recognizable manner. The present invention relates to a method of manufacturing a flip-chip type semiconductor device comprising: a step A of laminating on a semiconductor wafer a film for the backside of a flip-chip type semiconductor, in which the film is to be formed on the backside of a semiconductor element that is flip-chip connected onto an adherend; a step B of dicing the semiconductor wafer; and a step C of laser marking the film for the backside of a flip-chip type semiconductor, wherein the film for the backside of a flip-chip type semiconductor in the step C is uncured.

Abstract: A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts.

Abstract: A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.

Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region.

Abstract: A semiconductor light-emitting device includes first and second semiconductor layer and a light-emitting layer between the first and second semiconductor layers. These layers are on a conductive substrate. A first electrode and a first electrode pad, which are electrically connected to each other, are the first semiconductor layer. A second electrode is between the substrate and the second semiconductor layer. A portion of the second electrode is not covered by the first semiconductor, second semiconductor, and light-emitting layers. A second electrode pad is on the exposed portion of the second electrode. The second electrode pad has a planar area that is less than a planar area of the first electrode pad. A third electrode is on a second surface of the conductive substrate such that the conductive substrate is between the third electrode and the second electrode. The third electrode is electrically connected to the second electrode pad.

Abstract: A semiconductor device has a substrate and a gate formed over the substrate. An LDD region is formed in the substrate adjacent to the gate. A superjunction is formed in the LDD region while a portion of the LDD region remains between the superjunction and gate. A mask is formed over the substrate. A first region is doped with a first type of dopant using the mask. A stripe is doped with a second type of dopant using a portion of the mask. A drain contact region is formed in the substrate. The first region extends to the drain contact region. The first region and stripe are formed using chain implants. A source field plate and drain field plate are formed over the substrate. A trench is formed in the substrate. A source contact region is formed in the trench.

Abstract: An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract: Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract: A method of stacking a plurality of first dies to a respective plurality of second dies, each one of the first dies having a surface including a surface coupling region which is substantially flat, each one of the second dies having a respective surface including a respective surface coupling region which is substantially flat, the method comprising the steps of: forming, by means of a screen printing technique, an adhesive layer on the first dies at the respective surface coupling regions; and arranging the surface coupling region of each second die in direct physical contact with a respective adhesive layer of a respective first die among said plurality of first dies.

Abstract: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.

Abstract: An active matrix substrate (5) is provided with: a plurality of source wiring lines (S) and a plurality of gate wiring lines (G) which are arranged in a matrix; and pixels (P) having thin film transistors (25) disposed in the vicinity of the intersections of the source wiring lines (S) and the gate wiring lines (G), and pixel electrodes (26) connected to the thin film transistors (25). In the active matrix substrate (5), a base material (5a) is disposed in such a manner that the source wiring lines (S) and the gate wiring lines (G) intersect each other, and on the base material (5a), auxiliary capacity electrodes (28), which are provided on the pixel basis, are made of transparent electrodes, and generate an auxiliary capacity, and auxiliary capacity wiring lines (29), which are connected to the auxiliary capacity electrodes (28) and are made of an aluminum alloy, are provided.