Patents Examined by Hung Vu
  • Patent number: 9275858
    Abstract: A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: March 1, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9269617
    Abstract: A circuit device is configured with robust circuit connectors. In connection with various example embodiments, an integrated circuit device includes one or more via network layers below a bond pad contact, connecting the bond pad contact with one or more underlying metal layers. Each via network layer includes a plurality of via strips extending about parallel to the bond pad contact and in different directions to structurally support the bond pad contact.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: February 23, 2016
    Assignee: NXP B.V.
    Inventors: Yuan Li, Som Nath, Maarten van Dort
  • Patent number: 9263495
    Abstract: A method of fabricating an image sensor is provided. The method may include preparing a substrate with first to third pixel regions, coating a first color filter layer on the substrate, sequentially forming a first sacrificial layer and a first protection layer to cover the first color filter layer, forming a first photoresist pattern on the first protection layer to be overlapped with the first pixel region, performing a first dry etching process using the first photoresist pattern as an etch mask to the first sacrificial layer and the first protection layer to form a first color filter, a first sacrificial pattern, and a first protection pattern sequentially stacked on the first pixel region, and selectively removing the first sacrificial pattern to separate the first protection pattern from the first color filter.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungkwan Kim, Soo-Kyung Kim, Jung-kuk Park, Myung-Sun Kim, Jaesung Yun, Junetaeg Lee, Hakyu Choi
  • Patent number: 9252174
    Abstract: There is provided a solid-state imaging apparatus including a plurality of photoelectric conversion regions which photoelectrically convert light incident from a rear surface side of a semiconductor substrate, element isolation regions formed between the plurality of photoelectric conversion regions arranged in a matrix shape, and shielding members formed on upper surfaces of the element isolation regions. The element isolation regions have high impurity concentration regions of a high impurity concentration connected to at least a part of the shielding members.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: February 2, 2016
    Assignee: SONY CORPORATION
    Inventor: Yusuke Tanaka
  • Patent number: 9240390
    Abstract: A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: January 19, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shun Meen Kuo, Paul R. Hart, Margaret A. Szymanowski
  • Patent number: 9236491
    Abstract: A field effect transistor including: a gate insulating film; an oxide semiconductor layer that serves as an active layer and whose main structural elements are Sn, Zn and O, or Sn, Ga, Zn and O; and an oxide intermediate layer that is disposed between the gate insulating film and the oxide semiconductor layer, and whose resistivity is higher than that of the oxide semiconductor layer.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: January 12, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Masahiro Takata, Atsushi Tanaka
  • Patent number: 9236454
    Abstract: A method of fabricating a thin-film transistor, the method including: film-forming an active layer, that contains as a main component thereof an oxide semiconductor structured by O and at least two elements among In, Ga and Zn, in a film formation chamber into which at least oxygen is introduced, and b) heat treating the active layer at less than 300° C. in a dry atmosphere, wherein the film-forming a) and the heat treating are carried out such that, given that an oxygen partial pressure with respect to an entire pressure of an atmosphere within the film formation chamber in the film-forming is PO2depo (%), and an oxygen partial pressure with respect to an entire pressure of an atmosphere during the heat treating is PO2anneal (%), the oxygen partial pressure PO2anneal (%) at the time of the heat treating b) satisfies a relationship: ?20/3PO2depo+40/3?PO2anneal??800/43PO2depo+5900/43.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: January 12, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Masashi Ono, Masahiro Takata, Atsushi Tanaka, Masayuki Suzuki
  • Patent number: 9230805
    Abstract: A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: January 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9224778
    Abstract: There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: December 29, 2015
    Assignee: SONY CORPORATION
    Inventor: Toshifumi Wakano
  • Patent number: 9224933
    Abstract: A package for mounting a light emitting device thereon. The package includes a substrate, a light emitting device mounting part including a wiring formed on one surface of the substrate, the wiring including two areas that are arranged facing each other and being separated a predetermined interval apart from each other in a plan view, first and second through-wirings that penetrate the substrate and are provided on the two areas, respectively, each of the first and second through-wirings including one end electrically connected to the light emitting device mounting part and another end exposed from another surface of the substrate. A part of each of the first and second through-wirings includes a maximum part having a plan-view shape that is larger than a plan-view shape of the one end of each of the first and second through-wirings.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: December 29, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tsukasa Nakanishi, Atsushi Nakamura, Takayuki Matsumoto
  • Patent number: 9224819
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer formed of a III-V group nitride semiconductor, a first silicon nitride film formed on the semiconductor layer, a gate electrode formed on the first silicon nitride film, a source electrode and a drain electrode formed on the semiconductor layer such that the gate electrode is interposed between the source electrode and the drain electrode, and a second silicon nitride film formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode and having an oxygen atom density lower than that of the first silicon nitride film.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Miki Yumoto
  • Patent number: 9224818
    Abstract: A semiconductor device of an embodiment includes a semiconductor layer formed of a III-V group nitride semiconductor, a first silicon nitride film formed on the semiconductor layer, a gate electrode formed on the first silicon nitride film, a source electrode and a drain electrode formed on the semiconductor layer such that the gate electrode is interposed between the source electrode and the drain electrode, and a second silicon nitride film formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode and having an oxygen atom density lower than that of the first silicon nitride film.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Miki Yumoto
  • Patent number: 9214458
    Abstract: In a semiconductor device having a built-in Schottky barrier diode as a reflux diode, a maximum unipolar current is increased in a reflux state and a leakage current is reduced in an OFF state. A Schottky electrode is provided in at least a part of a surface between adjacent well regions of a second conductivity type disposed on a surface layer side of a drift layer of a first conductivity type, and an impurity concentration of a first conductivity type in a first region provided in a lower part of the Schottky electrode and provided between the adjacent well regions is set to be higher than a first impurity concentration of a first conductivity type in the drift layer and to be lower than a second impurity concentration of a second conductivity type in the well region.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: December 15, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
  • Patent number: 9190394
    Abstract: An LED module has an electrically insulating main body, a base surface and a mounting surface located opposite the base surface. A number of electrical connection contacts are arranged at the mounting surface. The connection contacts do not adjoin the base surface. A heat sink is arranged in the main body. The heat sink extends from the mounting surface as far as the base surface. Furthermore, the LED module has a number of LED chips, each having an electrically insulating carrier substrate at a chip underside and two chip contacts at a chip top side. The LED chips are arranged with the electrically insulating carrier substrate on the heat sink.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: November 17, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Frank Singer, Michael Zitzlsperger, Stefan Groetsch
  • Patent number: 9190481
    Abstract: A method is provided for fabricating transistors. The method includes providing a substrate; and forming at least one dummy gate structure having a dummy gate dielectric layer and a dummy gate electrode layer on the substrate. The method also includes forming a dielectric film on the substrate and the dummy gate structure; and performing a thermal annealing process onto the dielectric film to increase the density of the interlayer dielectric film. Further, the method includes planarizing the dielectric film having the increased density until the top surface of the dummy gate structure is exposed; and forming a dense layer having an increased density on the dielectric film having the increased density. Further, the method also includes removing the dummy gate dielectric layer and the dummy gate electrode layer to form an opening; and forming a gate dielectric layer and a gate electrode layer sequentially in the opening.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 17, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jie Zhao
  • Patent number: 9184420
    Abstract: Embodiments described herein may provide for devices comprising a digitized OLED light source (900) and/or methods of manufacturing such devices. In some embodiments, a first method may be provided. The first method may include the steps of depositing a first conductive layer (902) over a substrate (901), depositing a first organic layer (904) comprising electroluminescent material over the first conductive layer, and depositing a first patterned image layer (903) over some but not all of the first conductive layer. The first patterned image layer may locally alter the emissive properties of the first organic layer, and the shape of the first patterned image layer may be based on a non-uniform visual image. The first method may further comprise the step of depositing a second conductive layer (905) over the first organic layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 10, 2015
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Emory Krall, Huiqing Pang, Ruiqing Ma, Peter Levermore
  • Patent number: 9184205
    Abstract: There is provided a back-illuminated type solid-state image pickup unit, in which a pad wiring line is provided on a light reception surface, capable of improving light reception characteristics in a photoelectric conversion section by thinning an insulating film in the back-illuminated type solid-state image pickup unit. A solid-state image pickup unit according to the present technology to accomplish such a purpose includes a sensor substrate having a pixel region in which photoelectric conversion sections are formed in an array, and a drive circuit is provided on a surface opposed to a light reception surface for the photoelectric conversion sections of the sensor substrate. Moreover, a through hole via reaching the drive circuit from the light reception surface of the sensor substrate is provided in a peripheral region located outside the pixel region. Further, a pad wiring line directly laminated on the through hole via is provided on the light reception surface in the peripheral region.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 10, 2015
    Assignee: SONY CORPORATION
    Inventor: Kentaro Akiyama
  • Patent number: 9178102
    Abstract: A light emitting apparatus includes a translucent substrate, and a light emitting section and an optical filter section arranged in a first region of the substrate when viewed in a normal direction of a first surface of the substrate. The light emitting section has a laminate structure that includes, on the first surface of the substrate, a dielectric multilayer film, a first electrode, a functional layer with a light emitting layer, and a second electrode having semi-transmissive reflectivity. The optical filter section has a laminate structure that includes, on the first surface of the substrate, the dielectric multilayer film, the functional layer, and the second electrode. The dielectric multilayer film and the functional layer extend over the first region.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: November 3, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Tetsuji Fujita, Hidetoshi Yamamoto, Hideto Ishiguro, Tsukasa Eguchi
  • Patent number: 9165866
    Abstract: The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: October 20, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Xiaotian Zhang, Yan Xun Xue, Anup Bhalla, Jun Lu, Kai Liu, Yueh-Se Ho, John Amato
  • Patent number: 9159634
    Abstract: A transistor outline housing is provided that has bonding wires on an upper surface. The bonding wires are reduced in length and have connection leads with an excess length at an end opposite the bonding end.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 13, 2015
    Assignee: SCHOTT AG
    Inventors: Robert Hettler, Kenneth Tan, Georg Mittermeier, Karsten Droegemueller