Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a three dimensional helically shaped common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.

Abstract: A manufacturing method is a method for manufacturing a light emitting apparatus including a translucent substrate, and a light emitting section and an optical filer section that are arranged in a first region of the substrate when viewed in a normal direction of a first surface of the substrate. The manufacturing method includes: forming a dielectric multilayer film over the first region of the substrate; forming a first electrode on the dielectric multilayer film included in the light emitting section; forming a functional layer with a light emitting layer over the first electrode and the dielectric multilayer film included in the optical filter section; and forming a second electrode having semi-transmissive reflectivity on the functional layer over the first region of the substrate.

Abstract: Provided is a light-emitting device which can emit monochromatic light with high purity due to a microcavity effect and which can emit white light in the case of a combination of monochromatic light. Provided is a high-definition light-emitting device. Provided is a light-emitting device with low power consumption. In a light-emitting device with a white-color filter top emission structure, one pixel is formed of four sub-pixels of RBGY, an EL layer includes a first light-emitting substance which emits blue light and a second light-emitting substance which emits light corresponding to a complementary color of blue, and a semi-transmissive and semi-reflective electrode (an upper electrode) is formed so as to cover an edge portion of the EL layer.

Abstract: A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract: A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to expose the encapsulant. Removing the first portion also leaves a second portion of the shielding frame over the semiconductor die as shielding from interference. A third portion of the shielding frame around the semiconductor die provides a conductive pillar. A first interconnect structure is formed over a first side of the encapsulant, shielding frame, and semiconductor die. The sacrificial substrate is removed. A second interconnect structure over the semiconductor die and a second side of the encapsulant. The shielding frame can be connected to low-impedance ground point through the interconnect structures or TSV in the semiconductor die to isolate the die from EMI and RFI, and other inter-device interference.

Abstract: According to one embodiment, a semiconductor device includes: a first region including: a first semiconductor layer; a first semiconductor region; a second semiconductor region; a third semiconductor region having higher impurity concentration than the first semiconductor region; a first electrode; a second electrode; an insulating film; a third electrode; a fourth electrode, a second region including a pad electrode, and the third region including: the first semiconductor layer; the first semiconductor region; a third semiconductor region; the first electrode; the second electrode; and a first insulating layer.

Abstract: There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers.

Abstract: A FinFET comprises a substrate, an array of substantially parallel fins formed on the substrate and extending in a first direction, and an array of gates on the fins. First gates extend across the same fins of a first plurality of the fins in a second direction transverse to the first. Second gates extend across the same fins of a second plurality of fins in the second direction; the second gates having a length that is larger than that of the first gates. Third gates extend across the same fins of a third plurality of fins in the second direction; the third plurality of fins being located between the first and second pluralities. The third gates provide a transition between the first gates and the second gates in which a first portion of the third gates are dummies and a second portion are active devices such as pass gates.

Abstract: Among other things, one or more image sensors and techniques for forming such image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises a calibration region configured to detect a color level for image reproduction, such as a black calibration region configured to detect a black level for an image detected by the photodiode array. The image sensor comprises a dielectric film that is formed over the photodiode array and the calibration region. The dielectric film is configured to balance stress between the photodiode and the calibration region in order to improve accuracy of the calibration region.

Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.

Abstract: A light receiving region includes a plurality of light detecting sections 10. The light detecting sections 10 has a second contact electrode 4A. The second contact electrode 4A is arranged at a position overlapping a first contact electrode 3A, so as to contact the first contact electrode. Further, a resistive layer 4B is continued to the second contact electrode 4A.

Abstract: A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.

Abstract: According to one embodiment, a memory device, includes: a stacked body including first electrode layers stacked alternately with first insulating layers; a selection gate stacked body including selection gate electrode layers stacked alternately with second insulating layers in a stacking direction of the stacked body; a semiconductor member provided inside the stacked body and the selection gate stacked body, the semiconductor member extending in the stacking direction; a memory film provided between the semiconductor member and each of the f first electrode layers; and a gate insulator film provided between the semiconductor member and each of the selection gate electrode layers. Selection transistors are provided on the stacked body, the plurality of selection transistors included the selection gate electrode layers, the gate insulator film, and the semiconductor member, at least two of the selection transistors have mutually different threshold potentials.

Abstract: A back-illuminated type solid-state image pickup unit in which a pad wiring line is provided on a light reception surface and which is capable of improving light reception characteristics in a photoelectric conversion section by having a thinner insulating film in a pixel region. The solid-state image pickup unit includes a sensor substrate having a pixel region in which photoelectric conversion sections are formed in an array, and a drive circuit is provided on a surface opposed to a light reception surface for the photoelectric conversion sections of the sensor substrate. A through hole via reaching the drive circuit from the light reception surface of the sensor substrate is provided in a peripheral region located outside the pixel region. A pad wiring line directly laminated on the through hole via is provided on the light reception surface in the peripheral region.

Abstract: According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.

Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Abstract: A method for forming a photo diode is provided. The method includes: forming a first pair of electrodes and a second pair of electrodes over a substrate by using a conductive layer; forming a dielectric layer over the substrate; patterning the dielectric layer over the substrate; forming a photo conversion layer over the substrate; and forming a color filter layer over the photo conversion layer, wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a first pixel from a second portion of the color filter layer corresponding to a second pixel, and a refractive index of the dielectric layer is lower than a refractive index of the color filter layer, wherein the first pair of electrodes corresponds to the first pixel and the second pair of electrodes corresponds to the second pixel.

Abstract: A non-breakable display device, electronic appliance, or lighting device is provided. A bendable display device in which a first flexible substrate and a second flexible substrate provided with transistors overlap each other with a bonding layer therebetween is fabricated. The display device is bent so that the first substrate is positioned on the inner side (the valley side) and the second substrate is positioned on the outer side (the mountain side).