Abstract: The present invention relates to improved cooling of an electronic component loaded to a Printed Circuit Board, wherein the PCB comprises at its upper side at least one electronic component, and at least one Heat Conducting Member inserted into a through-hole of the PCB, wherein the HCM extends from the upper side to the lower side of the PCB and has a thermal contact to the component.

Abstract: The invention relates to a power plane system for suppressing ground bounce noise. The power plane system of the invention comprises a substrate, a power layer and a ground layer. The power layer comprises a plurality of metal units. There is a distance between two adjacent metal units. A plurality of bridges is used for connecting the metal units. The ground layer has a grounding metal plate. According to the invention, when the ground bounce noise occurs, the metal units can broaden the stop-band bandwidth. Therefore, the signals in the stop-band hardly are transmitted so as to suppress the ground bounce noise, and the high frequency ground bounce noise and the electromagnetic radiation can be suppressed efficiently.

Abstract: A film having a recess provided in a surface of the film is provided. The recess included a first portion and a second portion connected with the first portion. The second portion is deeper than the first portion. The recess in the film is filled with a conductive paste so as to fill the first portion and the second portion of the recess with a first portion and a second portion of the conductive paste, respectively. Then, the surface of the film is attached onto a surface of a substrate. The conductive paste is transferred to the surface of the substrate by removing the film from the substrate so as to transfer the first portion and the second portion of the conductive paste to the surface of the substrate. The transferred first portion and the transferred second portion of the conductive paste are baked to provide a first portion and the second portion of a conductor pattern, respectively. An insulating layer is provided on the conductor pattern.

Abstract: This invention relates to semiconductor devices and to printed circuit boards (PCB) or circuit assemblies used to electrically connect components. Delay devices are associated with the conductive traces or with integrated circuits. Delay is used to offset then realign the wave edges of propagating signals so as to minimize electric field effects on nearby signals. Impedance controlling devices are used to minimize reflections. The effects of split planes may be minimized or negated.

Abstract: A circuit board assembly includes a printed circuit board (PCB). The PCB has a pad layout which includes a set of pads arranged in a two-dimensional array having at least two pads in a first direction and at least two pads in a second direction that is substantially perpendicular to the first direction. Each pad has (i) a central portion and (ii) multiple lobe portions integrated with the central portion and extending from the central portion of that pad. The circuit board assembly further includes a circuit board component mounted to the pad layout via a set of solder joints. The above-described pad layout (or land pattern) is well-suited for soldering to a variety of AAP devices (e.g., either a CCGA device or a BGA device).

Abstract: In one embodiment, a pad is formed on a substrate surface. The pad is connected with a connecting pattern. A first mask is formed on the substrate. The first mask has a first opening exposing at least a portion of the pad and a portion of the connecting pattern. A second mask is formed on the first mask. The second mask has a second opening exposing at least a portion of the pad and a portion of the connecting pattern. A boundary surface or sidewall of the first opening is not coplanar with a boundary surface or sidewall of the second opening. Therefore, stresses may be prevented from concentrating on the boundary surface of the first opening, thereby allowing dispersion of the stresses and restraining pattern cracks.

Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

Abstract: A superconducting cable joint structure is a structure used to joint together superconducting cables used at cryogenic temperature or to joint together a terminal of the superconducting cable and a normal conducting cable, and it includes a joint insulation layer arranged radially outer than a portion connecting the superconducting cables' respective conductors together or the superconducting cable's conductor and the normal conducting cable's conductor together, and at least one coolant path provided at the joint insulation layer to cool the portion connecting the conductors together. The cable cores can have their connection prevented from generating heat to have an increased temperature.

Abstract: A superconducting cable has a plurality of superconducting wires wound around a core material (former) in a multilayered manner. The superconducting wires employ a twisted filament type superconducting wire having spiral superconducting filaments and an untwisted filament type superconducting wire having straight superconducting filaments. The layer in which an applied magnetic field is large and of which the low loss effect is expected is formed of twisted filament type superconducting wires, and the other layers are formed using the untwisted filament type superconducting wires; thus the AC loss can be reduced effectively. Thus, in the superconducting cable, the AC loss can be effectively reduced while a degradation of the current characteristics and the increase of cost are suppressed.

Abstract: The present invention is characterized in that in a metal-core multilayer printed wiring board (1) which is obtained by forming one or more of at least inner layers of a laminate having a insulating layer and a conductor layer stacked alternately from a metal plate and has the metal plate as a core, the metal plate (13) is disposed below a site on which a heating element (10) is to be mounted, a surface layer over which the heating element (10) is to be mounted is connected to the metal plate (13) of the inner layer via a BVH (12) and a heat radiation layer (14) is formed over the surface layer. The present invention makes it possible to efficiently radiate heat, which has been released from the heating element, to the outside of the printed wiring board without impairing the packaging density of circuits and at the same time, to mount another element on the side opposite to the side on which the heating element exists.

Abstract: A substrate supporting a plurality of interconnecting patterns arranged in matrix is cut at a position at least between adjacent columns of the interconnecting patterns. A plurality of positioning marks are formed on the substrate and arranged on a straight line between adjacent columns of the interconnecting patterns. Cutting of the substrate is performed by using the positioning marks as reference.

Abstract: A substrate structure including a substrate with solder bumps on a main region and a peripheral region of a front side thereof; a solder mask is formed over the front side of the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly therefrom, dividing the solder mask into separate areas. A method of underfilling a chip wherein a chip having a pattern of solder bumps formed on the underside of the chip is placed underside first onto the metal trace structure of the present invention. The solder bump pattern includes openings over the metal trace structure. Underfill is introduced into the metal trace structure so that the underfill flows from the metal trace structure and between the solder bumps to underfill the chip.

Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: A semiconductor device includes a semiconductor chip and a substrate having an interconnecting pattern formed thereover. The substrate has the semiconductor chip mounted on one surface thereof. The substrate has an outline larger than the semiconductor chip. First terminals are formed in a region outside the region of the substrate in which the semiconductor chip is mounted. Second terminals are a part of the interconnecting pattern which exposes its surface opposite to its surface opposing the semiconductor chip in a region closer to a center of the substrate than the first terminals. The semiconductor chip is electrically connected to the first and second terminals.

Abstract: A conductor strip includes a first end portion soldered to a printed circuit board, and a second end portion welded to a rechargeable battery. The conductor strip also includes a connecting portion disposed between the first and the second end portions. The connecting portion has a smaller width than that of the first end portion so that the peeling force acting on the first end portion is alleviated.

Abstract: A flexible wiring board are formed by growing metal bumps using a mask film patterned by photolithography. Fine openings can be formed with good precision, therefore, fine metal bumps can be formed with good precision because laser beam is not used to form opening in a polyimide film. After metal bumps have been formed, the mask film is removed and a liquid resin material is applied and dried to form a coating, which is then cured into a resin film. The coating can be etched at surface portions during coating stage to exposed the tops of metal bumps.

Abstract: To provide a junction structure and a junction method for conductive projection advantageous in that a required reinforcement strength can be obtained while suppressing the amount of a reinforcing resin material supplied to prevent warpage due to curing shrinkage. A conductive projection is joined to the surface of a conductor portion formed at the same level as that of the surface of the insulating layer so that a root portion of the projection is surrounded by a fillet-form resin material. The resin material contains an activator which assists in the junction between the conductive projection and the conductor portion when the resin material is in an uncured state, and is fused by heating to wet and rise the root portion of the conductive projection so as to be in a fillet form. The resin material is cured by an ultraviolet light while excluding the resin material on the conductor portion.

Abstract: A printed circuit board with a circuit carrier zone, in which a circuit carrier (S) is located is disclosed. Conductor strips (LE1, LE2) of the printed circuit board (L) are directed towards a guide zone (F) of the printed circuit board (L). Auxiliary conductor strips (H1, H2) are located in the guide zone (F), said strips running substantially parallel to the outline of the circuit carrier zone. First contact sections of the auxiliary conductor strips (H1, H2) are connected to the ends of the conductor strips (L1, L2) that lie in front of the guide zone (F), by bonding links (B) that do not intersect. Second contact sections of the auxiliary conductor strips (H1, H2) are connected to the contact pads (K), by bonding links (B) that do not intersect.

Abstract: An I/O routing pattern method is disclosed, for use with heterogeneous printed circuit boards (PCBs), such as those embedded with a reinforcement material, for example, a fiberglass weave. Traces are routed on the PCB so as to reduce sensitivity to changes in the dielectric constant (Dk), which are brought about by the strands of reinforcement material contained within the PCB laminate. The method minimizes the local variations, such as the Dk, time of flight, and capacitance variations, that are observed with traditional routing methods on heterogeneous PCBs.

Abstract: The present invention features a novel design for forming a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.