Patents Examined by I B Patel
  • Patent number: 7012197
    Abstract: A multi-layer printed circuit board includes an insulation substrate; a surface conductive pattern disposed on a surface of the insulation substrate; and an inner conductive pattern embedded in the insulation substrate. The surface conductive pattern has a surface roughness on an insulation substrate side, the surface roughness of the surface conductive pattern being larger than that of the inner conductive pattern.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: March 14, 2006
    Assignee: Denso Corporation
    Inventors: Toshikazu Harada, Koji Kondo
  • Patent number: 7009115
    Abstract: A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array package is described. The ball grid array package includes a substrate material having a first side configured to receive a semiconductor chip and a second side having a plurality of conductive pads arranged in an array of rows and columns. The array of pads has at least one edge not fully populated with pads.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: March 7, 2006
    Assignee: Broadcom Corporation
    Inventors: Kevin L. Seaman, Vernon M. Wnek
  • Patent number: 7005585
    Abstract: Wiring electrodes are formed on a first principal surface of a base substrate. An insulation film partially covers the first principal surface of the base substrate and the wiring electrodes. The insulation film has opening portions where the base substrate and the wiring electrodes are not coated with the insulation film. An electronic component having bump electrodes is mounted on the mounting board by connecting the bump electrodes with the wiring electrodes in the opening portions. A gap between the first principal surface of the base substrate and the electronic component is filled with sealing resin. The opening portions are substantially orthogonal to the longitudinal direction of the wiring electrodes. The ratio of the minimum width of a portion of the base substrate exposed at each of the opening portions to the thickness of the insulation film may advantageously be greater than or equal to 2.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: February 28, 2006
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hiroyuki Ishizaki
  • Patent number: 7002080
    Abstract: A multilayer wiring board is composed of a core portion, a first wiring portion and a second wiring portion. The core portion includes a core insulating layer containing a carbon fiber material. The first wiring portion is bonded to the core portion and has a laminated structure including at least a first insulating layer and a first wiring pattern, the first insulating layer containing glass cloth. The second wiring portion is bonded to the first wiring portion and has a laminated structure including at least a second insulating layer and a second wiring pattern. The core portion, the first wiring portion and the second wiring portion are arranged in a stack.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: February 21, 2006
    Assignee: Fujitsu Limited
    Inventors: Motoaki Tani, Nobuyuki Hayashi, Tomoyuki Abe, Yasuhito Takahashi, Takashi Shuto
  • Patent number: 7002081
    Abstract: A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: February 21, 2006
    Assignee: PPG Industries Ohio, Inc.
    Inventors: Alan E. Wang, Kevin C. Olson, Thomas H. Di Stefano
  • Patent number: 6989969
    Abstract: An integrated lead suspension includes a solder ball that is placed between a lead wiring pad provided on a flexure of the suspension, and a bonding pad provided on a slider of a head gimbal section. The lead wiring pad and bonding pad are soldered by melting the solder ball. As a result, there is provided a recessed section into which a solder ball is placed by way of surface raised sections, using gravitational force, in the vicinity of the center line of the surface of the lead wiring pad. In this way the position of the solder ball is not displaced from the center line when a bonding pad and lead wiring pad are connected by means of a solder ball.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: January 24, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Tatsumi Tsuchiya, Yuhsuke Matsumoto, Takaaki Murokawa, Naoki Fujii, Takuya Satoh, Yasuhiro Mita, Hiroyasu Tsuchida, Yoshio Uematsu
  • Patent number: 6985335
    Abstract: An integrated lead suspension includes a solder ball that is placed between a lead wiring pad provided on a flexure of the suspension, and a bonding pad provided on a slider of a head gimbal section. The lead wiring pad and bonding pad are soldered by melting the solder ball. As a result, there is provided a recessed section into which a solder ball is placed by way of surface raised sections, using gravitational force, in the vicinity of the center line of the surface of the lead wiring pad. In this way the position of the solder ball is not displaced from the center line when a bonding pad and lead wiring pad are connected by means of a solder ball.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: January 10, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Tatsumi Tsuchiya, Yuhsuke Matsumoto, Takaaki Murokawa, Naoki Fujii, Takuya Satoh, Yasuhiro Mita, Hiroyasu Tsuchida, Yoshio Uematsu
  • Patent number: 6977346
    Abstract: The present invention provides a circuit board including a first conductor layer forming a plurality of conductive circuit traces for interconnecting electronic components. The circuit board includes a substrate for supporting the first conductor layer and a pedestal formed from the substrate for supporting at least one of the plurality of electronic components. The pedestal provides a heat conduction path for conducting heat away from the at least one of the plurality of electronic components and a aperture in the substrate adjacent the pedestal for allowing a fluid to pass through the substrate.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: December 20, 2005
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Vivek A. Jairazbhoy, Andrew Z. Glovatsky
  • Patent number: 6974915
    Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: William Louis Brodsky, Benson Chan, Michael Anthony Gaynes, Voya Rista Markovich
  • Patent number: 6972380
    Abstract: A printed wiring board having differential pair signal traces has increased spacing between signal-carrying vias and ground or power planes and/or is equipped with selectively placed ground vias to enhance the impedance matching of the signal traces.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: December 6, 2005
    Assignee: Brocade Communications Systems, Inc.
    Inventor: Michael K. T. Lee
  • Patent number: 6972383
    Abstract: A multilayered circuit board has good imbedding properties for circuit patterns, and an interlayer insulating material having superior adhesive force and interlayer insulating properties. In a multilayered circuit board wherein interlayer connection is achieved by the contact of minute pointed protrusions, provided on a first conductive circuit layer, with a second conductive circuit layer, interlayer insulation is achieved by a film having a three-layer structure, comprising a thermoplastic film inserted between a pair of thermosetting adhesive layers.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: December 6, 2005
    Assignee: Nippon Mektron, Ltd.
    Inventor: Fumio Akama
  • Patent number: 6972381
    Abstract: A semiconductor device and a method of manufacturing the semiconductor device includes: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern 10 and electrodes 22 are electrically connected, and the anisotropic conductive material 16 is spreading out beyond the semiconductor chip 20 and is cured in the region of contact with the semiconductor chip 20; and a third step in which the region of the anisotropic conductive material 16 other than the region of contact with the semiconductor chip 20 is heated.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: December 6, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 6972382
    Abstract: A multilayer circuit board (50) includes a plurality of substrate cores (34 and 44), an adhesive/bonding layer (55) between at least two among the plurality of substrate cores, and a microvia (35 and 45) in each of at least two of the plurality of substrate cores. The microvia includes a conductive interconnection (39) between a top conductive surface and a bottom conductive surface of each of the plurality of substrate cores and the microvia in a first substrate core is arranged to be inverted relative to a microvia in a second substrate core. The multilayer circuit board can further include a plated through-hole (54) through the plurality of substrate cores and the adhesive/bonding layer such that at least two among the top conductive surfaces (32 or 46) and the bottom conductive surfaces (36 or 42) of the plurality of substrate cores are connected.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: December 6, 2005
    Assignee: Motorola, Inc.
    Inventors: James A. Zollo, Nitin B. Desai
  • Patent number: 6972376
    Abstract: In order to provide a flexible oxide superconducting cable which is reduced in AC loss, tape-shaped superconducting wires covered with a stabilizing metal are wound on a flexible former. The superconducting wires are preferably laid on the former at a bending strain of not more than 0.2 %. In laying on the former, a number of tape-shaped superconducting wires are laid on a core member in a side-by-side manner, to form a first layer. A prescribed number of tape-shaped superconducting wires are laid on top of the first layer in a side-by-side manner, to form a second layer. The former may be made of a metal, plastic, reinforced plastic, polymer, or a composite and provides flexibility to the superconducting wires and the cable formed therewith.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: December 6, 2005
    Assignee: Southwire Company
    Inventors: Raburn L. Hughey, Uday K. Sinha, David S. Reece, Albert C. Muller
  • Patent number: 6969808
    Abstract: A multi-layer printed board including signal layers, each signal layer including a signal line, a through-hole, and a ground through-hole. The signal layer includes a land connecting the through-hole and the signal line. An external periphery of the land has a first portion farthest from a center of the land, and a second portion extending a shorter distance from the center of the land than the first portion. A portion of the external periphery of the land opposite to the ground through-hole closest to the center of the land is the second portion. Consequently, impedance matching can be improved even if a signal frequency is high.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: November 29, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yasuhiro Shiraki
  • Patent number: 6940024
    Abstract: Wiring patterns are made of a conductive material containing Ag particles that exhibit high conductivity. Connection terminals that are connected to the ends of part of the wiring patterns, respectively, are made of a conductive material containing conductive particles in each of which an Au coating layer is formed on the surface of a conductive core particle. The connection terminals are arranged parallel with each other at small intervals on a narrow insertion portion of a flexible insulative board without being covered with respective conductive coatings.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: September 6, 2005
    Assignee: Alps Electric Co., Ltd.
    Inventor: Yasushi Watanabe
  • Patent number: 6940023
    Abstract: The present invention provides a board ensuring no peel-off of a wall and a land, even if a part is soldered to the board with lead-free solder. The board 10 is comprised of N (N?3) layer patterns electrically insulated from one another, and is formed with a through-hole 14 into which an electrode 19 of an electronic part 18 is to be inserted. An external land 15 is formed on a surface of each of the first and N-th layer patterns. An electrically conductive layer 17 is formed on an inner wall of the through-hole 14 such that the electrically conductive layer is electrically connected to the external land 15 of each of the first and N-th layer patterns. The electronic part 18 is fixed in the through-hole 14 with lead-free solder 20 filled in the through-hole 14. At least one internal land 16 extending from the electrically conductive layer 17 is formed in the same layer as a M-th layer pattern (2?M?(N?1)). The internal land 16 is not electrically connected to the M-th layer pattern.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: September 6, 2005
    Assignee: NEC Corporation
    Inventors: Naomi Ishizuka, Eiichi Kono
  • Patent number: 6936775
    Abstract: Embodiments of the invention provide thermally actuatable switches and selectively configurable circuit boards which may employ such switches. A circuit board of one embodiment includes a substrate having board leads and a plurality of electrical connectors arranged adjacent a component site. Selectively configurable circuitry may be carried by the substrate and adapted to selectively couple selected ones of the electrical connectors to selected ones of the board leads. One or more trace may be associated with each of the electrical connectors and one or more of these traces may include a thermally actuatable switch that can be selectively closed. The thermally actuatable switch may comprise a gap between two conductive lengths of the conductive trace, an exposed switch surface, and a thermally responsive member that may wet the exposed switch surface when selectively heated above an activation temperature.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: August 30, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, David Kao
  • Patent number: 6936772
    Abstract: In order to provide a flexible oxide superconducting cable which is reduced in AC loss, tape-shaped superconducting wires covered with a stabilizing metal are wound on a flexible former. The superconducting wires are preferably laid on the former at a bending strain of not more than 0.2%. In laying on the former, a number of tape-shaped superconducting wires are laid on a core member in a side-by-side manner, to form a first layer. A prescribed number of tape-shaped superconducting wires are laid on top of the first layer in a side-by-side manner, to form a second layer. The former may be made of a metal, plastic, reinforced plastic, polymer, or a composite and provides flexibility to the superconducting wires and the cable formed therewith.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: August 30, 2005
    Assignee: Southwire Company
    Inventors: Raburn L. Hughey, Uday K. Sinha, David S. Reece, Albert C. Muller
  • Patent number: 6933449
    Abstract: A printed circuit board having at least one layer of conductive traces on an external surface has at least one preformed solder element placed on a conductive trace area of the printed circuit board requiring a greater than standard amount of solder. The at least one preformed solder element is reflowed to form a connection with the layer of printed solder.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: August 23, 2005
    Assignee: Intel Corporation
    Inventor: Dudi Amir