Abstract: An organic EL element comprises a supporting substrate 12 having a first side surface 12b and a second side surface 12c located opposite to the first side surface in the first direction, a first electrode-attached on the supporting substrate, an organic EL body 16 disposed on the first electrode, a second electrode 18 disposed extending from the first side surface to the second side surface and covering at least a part of the organic EL body, and a sealing member disposed on the second electrode, extending from the first side surface to the second side surface and sealing at least the organic EL body, each of the side surfaces 18a and 20a of the second electrode and the sealing member on the first side surface-side being made evened with the first side surface, and each of the side surfaces 18b and 20b of the second electrode and the sealing member on the second side surface-side being made evened with the second side surface, in the first direction.

Abstract: Embodiments are directed to two-dimensional electron gas (2DEG)-confined 2DEG devices and methods. One such device includes a substrate and a heterostructure on the substrate. The heterostructure includes a first semiconductor layer, a second semiconductor layer, and a 2DEG layer between the first and second semiconductor layers. The device further includes a 2DEG device having a conduction channel in the 2DEG layer. An isolation electrode overlies the heterostructure and at least partially surrounds a periphery of the 2DEG device. The isolation electrode, in use, interrupts the 2DEG layer in response to an applied voltage.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film that contains carbon on the first film, and processing the second film into a second pattern. The method further includes impregnating a metal element or a semiconductor element into the second pattern after the processing into the second pattern. The method further includes processing the first film into a first pattern using the second pattern after the impregnation of the metal element or the semiconductor element.

Abstract: The purpose of the present invention is to avoid an inflection point in Vg-Id characteristics of the Thin Film transistor, and to avoid step disconnection of the insulating film formed on the semiconductor layer in the display device. The concrete structure of the present invention is: a display device including a TFT substrate having a thin film transistor (TFT) comprising; the TFT having a channel width and a channel length, a gate insulating film formed on a gate electrode, a semiconductor layer formed on the gate insulating film, wherein the gate electrode, near its edge, has a first sloping surface having a first taper angle in a cross sectional view along the direction of the channel width, an edge of the semiconductor layer in the cross sectional view along the direction of the channel width lies on the first sloping surface of the gate electrode.

Abstract: There is provided a technique that includes a substrate processing apparatus, comprising a process chamber having a cylindrical space configured to accommodate a substrate; and a plurality of nozzles communicating with a gas supply pipe and discharging processing gas in the process chamber, the process chamber includes a cylindrical reaction tube; a cylindrical manifold; and a lid, the lid includes a protection plate; and an introduction hole, the manifold includes a protection liner on an inner face of the manifold such that a second gap is formed between the manifold and the protection liner, the first gap being formed to allow the purge gas flowing toward the manifold to be deflected by the inner face of the manifold and to flow into the second gap.

Abstract: The present disclosure relates to an array substrate and a method for repairing an array substrate.

Abstract: A method for manufacturing a display device is disclosed, the method at least includes the following step: Firstly, a temporary substrate is provided, a hydrogen containing structure is formed on the temporary substrate, a polymer film is formed on the hydrogen containing structure, and a display element is formed on the polymer film. Afterwards, a laser beam process is performed, to focus a laser beam on the hydrogen containing structure, and the temporary substrate is then removed.

Abstract: In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include providing a structured layer of a catalyst material on the substrate, the catalyst material may include a first layer of material arranged over the substrate and a second layer of material arranged over the first layer of material, wherein the structured layer of catalyst material having a first set of regions including the catalyst material over the substrate and a second set of regions free of the catalyst material over the substrate, and forming a plurality of groups of nanotubes over the substrate, each group of the plurality of groups of nanotubes includes a plurality of nanotubes formed over a respective region in the first set of regions.

Abstract: A semiconductor storage device includes a semiconductor substrate and a plurality of first wiring layers stacked above the semiconductor substrate in a first direction orthogonal to the semiconductor substrate, and extending in a second direction intersecting the first direction and parallel to the semiconductor substrate. The device further includes a first memory pillar including a semiconductor layer and a first insulation layer extending in the first direction, the first insulation layer provided between the plurality of first wiring layers and the semiconductor layer so as to contact the semiconductor layer, and charge storage layers provided respectively between the plurality of first wiring layers and the first insulation layer. One or more of the charge storage layers is in contact with the first insulation layer. A plurality of second insulation layers is provided between each of the plurality of first wiring layers and each of the charge storage layers.

Abstract: The present invention relates to a method for casting electronic components. The invention also relates to a curable compound that can be used as casting compound in the method. The casting compound contains at least one cross-linking component which is homogeneously distributed in the casting compound and can cross-link to at least two different cross-linked systems. A first of these networks has a higher cross-link density than a second cross-linked system, wherein the cross-linking to the first cross-linked system is triggered via an event other than the cross-linking to the second cross-linked system. During casting, the at least one cross-linking component of the casting compound is cured at least in part to the first cross-linked system in at least one first region spaced from the components and at least to the second cross-linked system in a second region enclosing and immediately surrounding the components.

Abstract: This invention discloses a semiconductor power device formed on an upper epitaxial layer of a first conductivity type supported on a semiconductor substrate. The semiconductor power device having a super junction structure with the epitaxial layer formed with a plurality of vertically extended doped columns of a second conductivity type. The semiconductor power device further comprises a plurality of transistor cells each of the transistor cells comprises a planar gate extending over a top surface and each of the planar gates further includes a middle trench gate extending vertically into the epitaxial layer from a middle portion of the planar gates. Each of the middle trench gates is surrounded by a source region of the first conductivity type encompassed in a body region of the second conductivity type extending substantially between two adjacent doped columns of the second conductivity type.

Abstract: A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

Abstract: A display device includes: a first substrate including a display region and a non-display region provided at at least one side of the display region; a plurality of pixel units provided in the display region on the first substrate; a metal pattern provided in the non-display region on the first substrate; and a second substrate opposite to the first substrate, the second substrate being joined with the first substrate to encapsulate the display region, wherein the metal pattern includes a material having a high reactivity with oxygen as compared with an organic material.

Abstract: A ferroelectric memory unit cell includes a series connection of select gate transistor that turns the ferroelectric memory unit cell on and off, and a ferroelectric memory transistor. Data is stored in a ferroelectric material layer of the ferroelectric memory transistor. The ferroelectric memory unit cell may be a planar structure in which both transistors are planar transistors with horizontal current directions. In this case, the gate electrode of the access transistor can be formed as a buried conductive line. Alternatively, the ferroelectric memory unit cell may include a vertical stack of vertical semiconductor channels.

Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.

Abstract: The wafer fabrication technique uses an ion implantation process on the back side of the wafer to control the shape of the wafer. At least one first dopant is implanted into a front side of a wafer to dope the wafer. At least one second dopant is implanted into a back side of the wafer in a dopant profile to create a back side structure, where the back side structure controls a shape of the wafer. A blank wafer is provided that has an undoped front side and a form shaping back side structure on the back side. A doped wafer is provided that has a dopant implanted on the front side and a form shaping back side structure on the back side that least partially offsets the strain in the wafer induced by the front side dopant.

Abstract: The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure.

Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole and including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a second connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the semiconductor chip, and an encapsulant encapsulating the semiconductor chip and having a cavity disposed above the inactive surface of the semiconductor chip.