Abstract: The present disclosure discloses a method of manufacturing a thin film transistor (TFT) array substrate including a step of preparing a patterned active layer on a base substrate, wherein the step includes: sequentially forming an amorphous silicon (a-Si) thin film layer and a boron-doped (B-doped) amorphous silicon germanium (a-SiGe) thin film layer on the base substrate; performing crystallization on the a-Si thin film layer and the B-doped a-SiGe thin film layer using a thermal annealing process to obtain a polycrystalline silicon (poly-Si) thin film layer and a B-doped polycrystalline silicon germanium (poly-SiGe) thin film layer; and forming the patterned active layer by using a photolithography process to etch the poly-Si thin film layer and the B-doped poly-SiGe thin film layer. The present disclosure further discloses a TFT array substrate and a display device including the TFT array substrate.

Abstract: An AMOLED display panel is provided. The AMOLED display panel includes a plurality of pixel structures arranged in a matrix and a plurality of power lines, configured to provide a driving power to the pixel structures, wherein two adjacent rows or two adjacent columns of the pixel structures is a period unit, each period unit is disposed corresponding to one of the power lines, the one of the power lines is disposed between the two adjacent rows or the two adjacent columns of the pixel structures, and the one of the power lines provides the driving power to the two adjacent rows or the two adjacent columns of the pixel structures disposed at two side of the one of the power lines. By practice of the disclosure, the amount of the power lines could be decreased, so high PPI (Pixels Per Inch) of the display panel could be achieved.

Abstract: Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates. In some embodiments, a method for solderless integration of multiple semiconductor dies on flexible substrates includes arranging one or a plurality of semiconductor dies on a first carrier, active side down, and then depositing a sacrificial material over them. In some embodiments, the method further includes removing the first carrier and then building a wafer-level redistribution layer (RDL) over the active side of the one or plurality of semiconductor dies and the sacrificial material. In some embodiments, the method includes patterning the wafer-level RDL to form an outline of a final module footprint and then applying a second carrier to the wafer-level RDL. In some embodiments, the method can also include removing the sacrificial material from the one or plurality of semiconductor dies and the wafer-level RDL to achieve an integration of the one or plurality of semiconductor dies.

Abstract: A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) includes at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.

Abstract: The present disclosure discloses a manufacturing method of a quantum dot structure including: providing a quantum dot film layer on a substrate; providing a first protection film on the quantum dot film layer; providing a patterned array on the first protection film; providing a second protection film on the first protection film and the patterned array to obtain an intermediate body; and performing an annealing process on the intermediate body to obtain the quantum dot structure on the substrate.

Abstract: A flexible display panel is provided, including a flexible base, a barrier layer, a buffer layer, an active layer and a gate insulating layer, a gate metal layer and a second insulating layer, a second metal layer and an interlayer insulating layer, a second interlayer insulating layer, and a source/drain metal layer; on the second interlayer insulating layer, a first via hole is formed to communicate with the source/drain metal layer and the active layer, and a second contact hole is formed to communicate with the source/drain metal layer and the second interlayer insulating layer. A manufacturing method of a flexible display panel and a display apparatus including the display panel are also provided. The disclosure can ensure the normal display of the flexible display panel during the bending process.

Abstract: Provided is a wavelength conversion member that can be adjusted in chromaticity with high accuracy and a production method therefor. A wavelength conversion member 1 having a first principal surface 1a and a second principal surface 1b opposed to each other includes a glass matrix 2 and phosphor particles 3 disposed in the glass matrix 2, wherein concentrations of the phosphor particles 3 in the first principal surface 1a and in the second principal surface 1b are lower than concentrations of the phosphor particles 3 in surface layer bottom planes 1c and 1d located 20 ?m inward from the first principal surface 1a and 20 ?m inward from the second principal surface 1b, respectively.

Abstract: Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.

Abstract: An inspection system includes a laser light source, an optical system for laser marking that irradiates a semiconductor device with laser light from a metal layer side, a control unit that controls the laser light source to control laser marking, a two-dimensional camera that detects light from the semiconductor device on a substrate side and outputs an optical reflection image, and an analysis unit that generates a pattern image of the semiconductor device, and the control unit controls the laser light source so that laser marking is performed until a mark image appears in a pattern image.

Abstract: A magnetic domain wall displacement type magnetic recording element including a first ferromagnetic layer including a ferromagnetic material, a magnetic recording layer configured to extend in a first direction crossing a laminating direction of the first ferromagnetic layer and including a magnetic domain wall, and a nonmagnetic layer sandwiched between the first ferromagnetic layer and the magnetic recording layer, wherein the first ferromagnetic layer has a magnetic flux supply region at least at a first end in the first direction.

Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

Abstract: To provide a novel method for manufacturing a semiconductor device. To provide a method for manufacturing a highly reliable semiconductor device at relatively low temperature. The method includes a first step of forming a first oxide semiconductor film in a deposition chamber and a second step of forming a second oxide semiconductor film over the first oxide semiconductor film in the deposition chamber. Water vapor partial pressure in an atmosphere in the deposition chamber is lower than water vapor partial pressure in atmospheric air. The first oxide semiconductor film and the second oxide semiconductor film are formed such that the first oxide semiconductor film and the second oxide semiconductor film each have crystallinity. The second oxide semiconductor film is formed such that the crystallinity of the second oxide semiconductor film is higher than the crystallinity of the first oxide semiconductor film.

Abstract: A display component packaging structure, a manufacturing method thereof, and a display device are provided. The display component packaging structure includes a base substrate, a display component arranged at a surface of the base substrate, a packaging cover plate covering the display component, and a heat dissipation layer arranged at a surface of the packaging cover plate adjacent to the display component. An orthogonal projection of the heat dissipation layer onto the base substrate at least partially overlaps an orthogonal projection of the display component onto the base substrate.

Abstract: Provided are: a composite polymer semiconductor having a mesh shape formed by mixing a conjugated polymer and an insulating polymer; and a method for producing same. A composite polymer having a mesh structure is produced by introducing a small quantity of a conjugated polymer to an insulating polymer. The produced composite polymer having a mesh structure increases charge mobility, minimizes visible light absorption through the introduction of the small quantity of the conjugated polymer, and thus can be used as a transparent and flexible organic electronic element.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: An apparatus for positioning micro-devices on a destination substrate includes a first support to hold a destination substrate, a second support to provide or hold a transfer body having a surface to receive an adhesive layer, a light source to generate a light beam, a mirror configured to adjustably position the light beam on the adhesive layer on the transfer body, and a controller. The controller is configured to cause the light source to generate the light beam and adjust the mirror to position the light beam on the adhesive layer so as to selectively expose one or more portions of the adhesive layer to create one or more neutralized portions. The transfer body and the destination substrate are moved away from each other and one or more micro-devices corresponding to the one or more neutralized portions of the adhesive layer remain on the destination substrate.

Abstract: An optoelectronic semiconductor component comprising a connection carrier with a mounting face and an electrically insulating base member. An optoelectronic semiconductor chip is arranged on the mounting face of the connection carrier. A radiation-transmissive body having four side faces is provided. The radiation-transmissive body surrounds the semiconductor chip in such a way that the radiation-transmissive body envelops outer faces of the optoelectronic semiconductor chip not facing the connection carrier in form-fitting manner. The radiation-transmissive body comprises at least one side face which extends at least in places at an angle of between 60° and 70° to the mounting face. The base member has a thickness which amounts to at most 250 ?m.

Abstract: Embodiments of the present application provide an Oxide TFT, a manufacturing method thereof, an array substrate and a display device. The Oxide TFT includes a base substrate; a gate electrode, a gate insulating layer and an active layer which are located on the base substrate; a source electrode and a drain electrode, the active layer is at least partly covered with the source electrode and the drain electrode; and a channel protection layer located between the source electrode and the drain electrode, each of the source electrode and the drain electrode includes at least part of a first metallic layer and at least part of a second metallic layer, the first metallic and the second metallic layer are stacked one on another, the channel protection layer is of a metal oxide.

Abstract: The present disclosure provides a pixel circuit structure and a display device using the same. The pixel circuit structure includes: a metal light shielding layer; at least one buffer layer formed on the metal light shielding layer; a thin film transistor formed on the at least one buffer layer; an insulating layer formed on a gate of the thin film transistor; and a second gate, formed on the insulating layer, forming a storage capacitance with the gate, and electrically coupled to a power line of the thin film transistor, wherein the metal light shielding layer is electrically coupled to the power line of the thin film transistor.