Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: forming a semiconductor feature on a first surface of a substrate; forming a first insulating film on the semiconductor feature; forming a first wiring layer on the first insulating film; forming a second insulating film on the first wiring layer; forming a second wiring layer on the second insulating film; forming a first electrode on the second wiring layer; providing a protective adhesive that covers the first electrode and the second wiring layer; bonding a supporting substrate onto the protective adhesive; polishing a second surface of the substrate opposite to the first surface; removing the supporting substrate from the protective adhesive; and removing at least a portion of the protective adhesive to expose the first electrode.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: A semiconductor device includes an insulating substrate, a semiconductor element, a conductor substrate, and a case member. The semiconductor element is connected above the insulating substrate, and the conductor substrate is connected above the semiconductor element. The case member surrounds a region overlapping with the insulating substrate, the semiconductor element, and the conductor substrate in plan view to avoid the region. A plurality of metal patterns are arranged on a main surface of an insulating layer. A groove is formed between a pair of adjacent metal patterns of the plurality of metal patterns. A through hole is formed in the conductor substrate at a position overlapping with the groove in plan view.

Abstract: Provided is a method capable of predicting the warpage caused when a silicon wafer is subjected to heat treatment taking into account the effect of oxygen and a method of producing a silicon wafer. The method includes: determining the mobile dislocation density, the stress, and the time evolution of the strain of the silicon wafer being subjected to heat treatment from the rate of change in the strain and the rate of change in the mobile dislocation density; and determining the magnitude of plastic deformation of the silicon wafer as a warpage. The mobile dislocation density Ni at the start of the heat treatment is given as: Ni=A×(?Oi×L?Lo)2.5??(1), where A and L0: constants, ?Oi: the concentration of oxygen used by oxygen precipitates in the silicon wafer at the start of the heat treatment, L: the mean size of the oxygen precipitates at the start of the heat treatment.

Abstract: Disclosed is a method for transient liquid-phase bonding between metal materials using a magnetic force. In particular, in the method, a magnetic force is applied to a transient liquid-phase bonding process, thereby shortening a transient liquid-phase bonding time between the metal materials, and obtaining high bonding strength. To this end, an attractive magnetic force is applied to a ferromagnetic base while a repulsive magnetic force is applied to a diamagnetic base, thereby to accelerate diffusion. This may reduce a bonding time during a transient liquid-phase bonding process between two bases and suppress formation of Kirkendall voids and voids and suppress a layered structure of an intermetallic compound, thereby to increase a bonding strength.

Abstract: In described examples, a first device on a first surface of a substrate is coupled to a structure arranged on a second surface of the substrate. In at least one example, a first conductor arranged on the first surface is coupled to circuitry of the first device. An elevated portion of the first conductor is supported by disposing an encapsulate and curing the encapsulate. The first conductor is severed by cutting the encapsulate and the first conductor. A second conductor is coupled to the first conductor. The second conductor is coupled to the structure arranged on the second surface of the substrate.

Abstract: A method of fabricating an electronic component with multiple quantum islands is provided, including supplying a substrate on which rests a nanowire made of semiconductor material not intentionally doped, the nanowire having at least two main control gates resting thereon so as to form respective qubits in the nanowire under the two main control gates, the two main control gates being separated by a groove, top and lateral faces of the two main control gates and a bottom of the groove being covered by a dielectric layer; depositing a conductive material in the groove and on the top of the two main control gates; and planarizing down to the dielectric layer on the top of the two main control gates, so as to obtain an element made of conductive material self-aligned between the main control gates.

Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, a core dielectric layer disposed on the chip package, and an antenna pattern disposed on the core dielectric layer opposite to the chip package. The chip package includes a semiconductor chip, an insulating encapsulation encapsulating the semiconductor chip, and a redistribution structure electrically coupled to the semiconductor chip. The redistribution structure includes a first circuit pattern located at an outermost side of the chip package, and a patterned dielectric layer disposed between the first circuit pattern and the insulating encapsulation. The core dielectric layer is in contact with the first circuit pattern. The core dielectric layer and the patterned dielectric layer are of different materials. The antenna pattern is electrically coupled to the chip package.

Abstract: The present invention relates to organic light-emitting devices comprising (a) an anode, (i) a cathode, and (e) an emitting layer between the anode and cathode, comprising 2 to 40% by weight of a luminescent organometallic complex X having a difference of the singlet energy (ES1(X)) and the triplet energy (ET1(X)) of of ?0.3 eV [?(ES1(X))?(ET1(X))?0.3], 0.05 to 5.0% by weight of a fluorescent emitter Y and 55 to 97.95% by weight of a host compound(s), wherein the amount of the organometallic complex X, the fluorescent emitter Y and the host compound(s) adds up to a total of 100% by weight and the singlet energy of the luminescent organometallic complex X (ES1(X)) is greater than the singlet energy of the fluorescent emitter Y (ES1(Y)) [(ES1(X))>ES1(Y)].

Abstract: The present technology relates to an imaging element, an imaging apparatus, and electronic equipment which are capable of accurately detecting phase difference. The imaging element includes a first light-receiving part that receives incident light entering through a first on-chip lens, a first phase detecting pixel which is placed between the first on-chip lens and the first light-receiving part and which has a shading film to limit an amount of light reaching the first light-receiving part, and a second phase detecting pixel which has a second light-receiving part to receive incident light entering through a second on-chip lens, with the second light-receiving part being divided into a plurality of light-receiving regions. The technique disclosed herein is applicable to imaging apparatuses having the autofocusing function.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the following steps. A fin structure having a base and a plurality of fin portions extending away from the base is provided. A portion of the fin structure in a first region is removed to form a first trench in the base and a first bump formed in the first trench. A first oxide layer is formed in the first region. The first oxide layer is removed.

Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

Abstract: A light emitting diode (LED) device includes a light emitting epitaxial layer having opposite first and second surfaces and a plurality of microlenses formed on the first surface. The light emitting epitaxial layer includes a first type semiconductor layer defining the first surface, a second type semiconductor layer defining the second surface, and a light emitting layer disposed between the first and second type semiconductor layers and spaced apart from the first and second surfaces. The microlenses are formed on the first surface and formed of a light transmissible substrate for epitaxial growth of the light emitting epitaxial layer. A method for manufacturing the light emitting diode device is also disclosed.

Abstract: An apparatus for light diffraction and an organic light emitting diode (OLED) incorporating the light diffraction apparatus is disclosed. An apparatus for light diffraction may comprise an optional planarization layer, a transparent substrate, a waveguide layer. The planarization layer may have a refractive index of ns. The transparent substrate may have a refractive index of ng. The waveguide layer may have a refractive index nw distributed over of the transparent substrate. The waveguide layer may comprise a binding matrix, at least one nanoparticle. The waveguide layer may be interposed between the transparent substrate and the optional planarization layer.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: There is provided a method of processing a substrate by a substrate processing apparatus including a substrate mounting table having a refrigerant passage and a heater, and a chiller. The method includes adjusting a temperature of the substrate mounting table to a first temperature to process the substrate; and adjusting the temperature of the substrate mounting table to a second temperature higher than the first temperature to process the substrate. The temperature of the substrate mounting table becomes the second temperature by allowing the refrigerant at a first flow rate to flow from the chiller to the refrigerant passage and operating the heater. The temperature of the substrate mounting table becomes the first temperature by allowing the refrigerant at a second flow rate larger than the first flow rate to flow from the chiller to the refrigerant passage and operating the heater, or stopping an operation of the heater.

Abstract: An organic EL element comprises a supporting substrate 12 having a first side surface 12b and a second side surface 12c located opposite to the first side surface in the first direction, a first electrode-attached on the supporting substrate, an organic EL body 16 disposed on the first electrode, a second electrode 18 disposed extending from the first side surface to the second side surface and covering at least a part of the organic EL body, and a sealing member disposed on the second electrode, extending from the first side surface to the second side surface and sealing at least the organic EL body, each of the side surfaces 18a and 20a of the second electrode and the sealing member on the first side surface-side being made evened with the first side surface, and each of the side surfaces 18b and 20b of the second electrode and the sealing member on the second side surface-side being made evened with the second side surface, in the first direction.

Abstract: Embodiments are directed to two-dimensional electron gas (2DEG)-confined 2DEG devices and methods. One such device includes a substrate and a heterostructure on the substrate. The heterostructure includes a first semiconductor layer, a second semiconductor layer, and a 2DEG layer between the first and second semiconductor layers. The device further includes a 2DEG device having a conduction channel in the 2DEG layer. An isolation electrode overlies the heterostructure and at least partially surrounds a periphery of the 2DEG device. The isolation electrode, in use, interrupts the 2DEG layer in response to an applied voltage.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film that contains carbon on the first film, and processing the second film into a second pattern. The method further includes impregnating a metal element or a semiconductor element into the second pattern after the processing into the second pattern. The method further includes processing the first film into a first pattern using the second pattern after the impregnation of the metal element or the semiconductor element.

Abstract: The purpose of the present invention is to avoid an inflection point in Vg-Id characteristics of the Thin Film transistor, and to avoid step disconnection of the insulating film formed on the semiconductor layer in the display device. The concrete structure of the present invention is: a display device including a TFT substrate having a thin film transistor (TFT) comprising; the TFT having a channel width and a channel length, a gate insulating film formed on a gate electrode, a semiconductor layer formed on the gate insulating film, wherein the gate electrode, near its edge, has a first sloping surface having a first taper angle in a cross sectional view along the direction of the channel width, an edge of the semiconductor layer in the cross sectional view along the direction of the channel width lies on the first sloping surface of the gate electrode.