Abstract: The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlyGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlyGaN layer to the junction between the i-GaN channel layer and the i-AlxGaN layer.

Abstract: Provided is a method of manufacturing a light emitting device, comprising: preparing a base body having a concave portion; disposing a light emitting element at the bottom of the concave portion; disposing a first resin containing first phosphor particles having an average particle size of 10 ?m or more and 30 ?m or less and a first filler having an average particle size of 5 ?m or more and 20 ?m or less to cover the light emitting element; centrifugally precipitating the first phosphor particles and the first filler toward the base body; temporarily curing the first resin; disposing a second resin containing second phosphor particles and a second filler having an average particle size of 5 nm or more and 100 nm or less on the first resin temporarily cured; centrifugally precipitating the second phosphor particles and the second filler toward the first resin; and curing the first and second resins.

Abstract: A display device includes: a plurality of organic layers each made of an organic material and each having a predetermined modulus of elasticity and a predetermined thickness; and a plurality of inorganic layers each made of an inorganic material and each having a predetermined modulus of elasticity and a predetermined thickness. The plurality of organic layers and the plurality of inorganic layers are stacked together to constitute a device body which forms the display device. A quotient obtained by dividing the sum of flexural rigidities of the plurality of inorganic layers by the sum total of the sum of flexural rigidities of the plurality of organic layers and the sum of the flexural rigidities of the plurality of inorganic layers is 0.78 or higher and 1 or lower.

Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

Abstract: A method of manufacturing a semiconductor device includes preparing a first wafer including a first trench; forming a first semiconductor layer inside the first trench so that a first space remains in the first trench; obtaining a first level corresponding to a bottom of the first space and a second level estimated by a size or a shape of the first space; preparing a second wafer including a second trench having a shape and a size substantially same as a shape and a size of the first trench; forming a second semiconductor layer inside the second trench in the second so that a second space remains in the second trench; forming a third semiconductor layer to fill the second space in the second trench; and removing a surface portion of the second wafer to a depth corresponding to a level between the first level and the second level.

Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.

Abstract: A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a first sacrificial film over a target layer to be etched, forming a first partition mask over the first sacrificial film, forming a first sacrificial film pattern by etching the first sacrificial film using the first partition mask, forming a first spacer at a sidewall of the first sacrificial film pattern, and forming a first spacer pattern by removing the first sacrificial film pattern. The first partition mask includes a plurality of first line-shaped space patterns extending in a first direction. A width of at least one space pattern located at both edges from among the plurality of first space patterns is smaller than a width of each of other space patterns.

Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Abstract: A display panel and a display device comprising the same are provided. The display panel includes a planar substrate and a boundary substrate formed by bending the boundary of the planar substrate; and scan lines arranged on the planar substrate and extended to the boundary substrate. The width of the scan line on the bended position of the planar substrate is larger than the width of the remaining scan line.

Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.

Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Abstract: The present invention relates to a method for manufacturing a nitrogen-face polarity gallium nitride epitaxial structure, which includes: providing a gallium nitride template which includes a substrate and a first nitrogen-face polarity gallium nitride layer positioned on the substrate; re-growing the gallium nitride on a surface of the first nitrogen-face polarity gallium nitride layer to form a second nitrogen-face polarity gallium nitride layer; and sequentially growing a barrier layer and a channel layer on the second nitrogen-face polarity gallium nitride layer. The method for manufacturing the nitrogen-face polarity gallium nitride epitaxial structure provided by the present application enables a simple growth of the nitrogen-face polarity gallium nitride, can effectively eliminate the radio frequency dispersion phenomenon, and is beneficial to large-scale production and utilization of the nitrogen-face polarity gallium nitride epitaxial structure.

Abstract: A method of manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. The second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.

Abstract: The present disclosure relates to three dimensional (3D) transistor structures and methods of forming the same. In an aspect, a method comprises providing a vertical stack of alternating layers of channel material and dummy material, forming a first set of fins on the stack, and forming a second fin above the first set of fins, the second fin extending orthogonal to the first set of fins. Further, the first set of fins is cut into a set of fin portions, using the second fin and a first sidewall spacers as an etch mask, and second sidewall spacers are formed on the second fin. These structures are used to form a 3D structure of channel regions and source/drain regions forming transistor structures. Advantageously, the 3D semiconductor structure is manufactured using a relatively low number of mask layers per transistor which decreases manufacturing costs.

Abstract: A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH3 bonds less than the first content of Si—CH3 bonds.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: This invention discloses an ESD protection circuit. The ESD protection circuit is arranged on a display panel. It comprises a first conductive via layer electrically connected with a first signal line for outputting signal and a second signal line for inputting signal, and a thin film transistor. A gate of the thin film transistor is electrically connected with a drain, and the second signal line is electrically connected with the gate and/or the drain of the thin film transistor, and the first signal line is electrically connected with a source of the thin film transistor. This invention also discloses a display panel and a display device. In the present invention, the disconnection of the signal line due to electrostatic breakdown is solved.

Abstract: A method of forming a chip package structure can include: forming a substrate; forming a first cavity in the substrate; and installing a first chip in the first cavity. The method can also include forming a second cavity in the substrate; and installing a second chip in the second cavity. The first cavity is located at a first side of the substrate, and the second cavity is located at a second side of the substrate, where the first side of the substrate is opposite to the second side of the substrate.

Abstract: A method of manufacturing array substrate and a display panel, wherein, the method of manufacturing array substrate includes: depositing a gate electrode, a gate insulation layer, a semiconductor layer, a metal layer and a photoresist; forming an non-exposure area, a partial exposure area and a full exposure area through exposure and developing; then, performing a first ashing treatment and a wet etching to form a metal layer recess, and performing a second ashing treatment to etch off residual photoresist which remains in the metal layer recess after the first ashing treatment; and finally performing a dry etching to form a pattern of a channel region.