Abstract: The present invention is a method for removing a portion of a liner film and a metallization layer superimposed over the liner film to expose an underlying dielectric layer on a semiconductor wafer. Specifically, at least a portion of the metallization layer is removed by chemical mechanical polishing the metallization layer using a first polishing slurry having a plurality of first abrasive particles and at least a portion of the liner film is removed by chemical mechanical polishing the liner film using a second polishing slurry having a plurality of second abrasive particles. The first abrasive particles and the second abrasive particles used in the polishing steps have different bulk densities.

Abstract: A semiconductor ceramic composed of barium titanate, lead titanate, strontium titanate, and calcium titanate as primary components, includes samarium oxide as a semiconductor-forming agent in the primary components, and the average diameter of crystalline particles of the semiconductor ceramic is about 7 to 12 &mgr;m. The semiconductor ceramic has a resistivity at room temperature not greater than 3.5 &OHgr;cm, a withstand voltage not less than 50 V/mm, a resistance-temperature coefficient &agr;10-100 not less than 9%/°C. and also has less variability of resistance.

Abstract: A planarization method is used in a dual damascene structure. At the stage that a dual damascene structure is semi-formed on a semiconductor substrate but before a planarization process, the planarization method starts by forming a dielectric layer on a metal layer, which is to be polished. A portion of the dielectric layer other than the dual damascene structure is removed by etching. A CMP process is performed to planarize the substrate and exposes an inter-metal dielectric layer.

Abstract: The present invention provides a multi-layer semiconductor memory device comprising: a bottom electrode having a bottom layer, an upper interface layer and an intermediate tuning layer disposed between the bottom layer and the upper interface layer; a top electrode; and a high dielectric constant dielectric layer disposed between the bottom electrode and the top electrode. The present invention further provides an apparatus and a method for manufacturing high density DRAMs having capacitors having high quality HDC materials and low leakage currents. Another aspect of the present invention provides an electrode-dielectric interface that nucleates high quality HDC films. The present invention further provides an apparatus and a method for manufacturing capacitors within a high aspect ratio aperture.

Abstract: The invention is a method of depositing an aluminum nitride comprising layer over a semiconductor substrate, a method of forming DRAM circuitry, DRAM circuitry, a method of forming a field emission device, and a field emission device. In one aspect, a method of depositing an aluminum nitride comprising layer over a semiconductor substrate includes positioning a semiconductor substrate within a chemical vapor deposition reactor. Ammonia and at least one of triethylaluminum and trimethylaluminum are fed to the reactor while the substrate is at a temperature of about 500° C. or less and at a reactor pressure from about 100 mTorr to about 725 Torr effective to deposit a layer comprising aluminum nitride over the substrate at such temperature and reactor pressure. In one aspect, such layer is utilized as a cell dielectric layer in DRAM circuitry. In one aspect, such layer is deposited over emitters of a field emission display.

Abstract: A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas and gas plasma. A first passivation layer is formed upon the adhesion layer, the first passivation layer and the gas and gas plasma including at least one common chemical element.

Abstract: A method for forming a thin film transistor having source and drain electrodes self-aligned to a gate electrode by employing a single lithographic step includes forming an opaque gate electrode on a substrate, depositing a first dielectric layer on the gate electrode and the substrate, depositing a semiconductor layer on the first dielectric layer, and depositing a second dielectric layer on the semiconductor layer. A first photoresist is deposited on the second dielectric layer and patterned by employing the gate electrode as a mask for blocking light used to expose the first photoresist. The second dielectric layer is etched to form a top insulator portion of the second dielectric layer in alignment with the gate electrode. The first photoresist is removed. A doped semiconductor layer and a conductive layer are deposited. A second photoresist is formed on the conductive layer.

Abstract: A method of manufacturing a semiconductor memory device, which includes: a step of laminating and flattening a first interlayer insulating film on a semiconductor substrate provided with a semiconductor element having a diffusion region and then forming a contact hole in the first interlayer insulating film on the semiconductor element, a step of forming a contact plug by burying a contact plug material into the contact hole, a step of laminating a first electrode material forming a lower electrode for a capacitor so as to cover at least the contact plug and forming a lower electrode on the contact plug by patterning using a first mask, a step of forming a second interlayer insulating film so as to cover the lower electrode, and flattening the second interlayer insulating film until the surface of the second interlayer insulating film reaches a height identical with the surface of the lower electrode, a step of forming a ferroelectric material film and a second electrode material film forming an upper electro

Abstract: A soft metal conductor for use in a semiconductor device which has an uppermost layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent polishing step. The invention also provides a method for making a soft metal conductor that has a substantially scratch-free surface upon polishing by a multi-step deposition process, i.e., first sputtering at a higher temperature and then sputtering at a lower temperature and followed by another high temperature sputtering process. The invention further discloses a method for forming a substantially scratch-free surface on a soft metal conductor by first depositing a soft metal layer at a low deposition temperature and then annealing the soft metal layer at a higher temperature to increase the grain size of the metal.

Abstract: A premold type semiconductor package includes a plurality of leads arranged side by side and having upper and lower common surfaces, a mold resin integrally molded with the leads for securing them from the upper and lower surfaces thereof. The mold resin defines a chip mounting recess at an upper side on the first surfaces of the leads, so that a semiconductor chip is to be mounted in the recess. The upper surfaces of the leads are partially exposed in the recess so as to define internal connecting terminals to which the semiconductor chip is to be electrically connected. The mold resin is provided with a plurality of holes by which the lower surfaces of the leads are partially exposed to define external connecting terminals.

Abstract: A method of manufacturing a semiconductor device, which comprises the steps of subjecting a solid material to a first treatment consisting of a thermal treatment and/or a chemical treatment thereby to obtain a treated solid material having desired properties, and adhering the treated solid material onto a substrate for the semiconductor device, thereby to form a thin film on the substrate.

Abstract: A method for forming an electrical contact for a semiconductor device comprises the steps of providing a semiconductor wafer section having a major surface with a plurality of conductive pads thereon and electrically coupling each pad with an elongated electrical interconnect. Next, each electrical interconnect is encased in a dielectric and the dielectric is sectioned to expose a portion of each interconnect. An inventive structure which can be formed by the inventive method is also described.

Abstract: An integrated circuit chip package is provided which incorporates one or more differential pairs of signal lines coupled to an integrated circuit chip. The differential pairs each include a first signal line and a second signal line. The first signal lines are non-coplanar with the second signal lines. The first signal lines of the differential pairs may be provided in a first plane. The second signal lines of the differential pairs may be provided in a second plane different from the first plane. A first ground plane is provided adjacent the first signal lines and a second ground plane is provided adjacent the second signal lines. The spacing of respective signal lines provides, among other things, the capability of having a greater density of differential pairs of signal lines within the planar area of an integrated circuit chip package.

Abstract: A method for fabricating dual damascene is to form an undoped silicate glass (USG) liner before forming a fluorinated silicate glass (FSG) layer which serves as an inter-metal dielectric (IMD) layer on a semiconductor substrate. As a result, the surface sensitivity is eliminated, while a FSG layer with a more uniform thickness and a higher reliability is obtained. In addition, the USG liner increases the adhesion between the FSG layer and other material layers, while no particles are easily formed thereon.

Abstract: A novel lead zirconium titanate (PZT) material having unique properties and application for PZT thin film capacitors and ferroelectric capacitor structures, e.g., FeRAMs, employing such thin film material. The PZT material is scalable, being dimensionally scalable, pulse length scalable and/or E-field scalable in character, and is useful for ferroelectric capacitors over a wide range of thicknesses, e.g., from about 20 nanometers to about 150 nanometers, and a range of lateral dimensions extending to as low as 0.15 &mgr;m. Corresponding capacitor areas (i.e., lateral scaling) in a preferred embodiment are in the range of from about 104 to about 10−2 &mgr;m2. The scalable PZT material of the invention may be formed by liquid delivery MOCVD, without PZT film modification techniques such as acceptor doping or use of film modifiers (e.g., Nb, Ta, La, Sr, Ca and the like).

Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.

Abstract: A fabrication method for a dynamic random access memory is described, wherein after the formation of the shallow trench in the substrate to define the active region, an isolation structure is formed in the shallow trench. A first conductive layer is formed to cover the substrate and to fill the shallow trench. A portion of the first conductive layer is removed, leaving only the portion in the shallow trench to form a bit line in the shallow trench. Thereafter, an elevated portion is formed on the substrate, connecting the bit line to the active region where the source region is to be formed. A transistor is then formed in the active region. The area of the source region of the transistor includes the substrate under the elevated part, wherein the source region is connected to the second conductive layer. A dielectric layer is further formed covering the substrate, followed by forming a capacitor on the dielectric layer, wherein the capacitor passes through the dielectric layer to connect with the transistor.

Abstract: Copper material is exposed on the surface of a TiN film (an underlying film) formed in the main surface of a silicon substrate with a silicon oxide film interposed. Subsequently, a thin copper film is formed on TiN film. Thus, the thin copper film can be formed on the film including metal with high melting point or nitride thereof with high adhesion by means of CVD.

Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti

Abstract: A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) CMP of dielectric layer underlying the metal following SOG planarization; 2) CMP of dielectric layer underlying the metal following formation of vias; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes.