Abstract: A process for fabricating a semiconductor device with copper interconnects is disclosed. In the process of the present invention, a layer of dielectric material is formed on a substrate. At least one recess is formed in the layer of dielectric material. Barrier layers and seed layers for electroplating are then deposited over the entire surface of the substrate. The recess is then filled with copper by electroplating copper over the surface of the substrate. The electroplated copper has an average grain size of about 0.1 &mgr;m to about 0.2 &mgr;m immediately after deposition. The substrate is then annealed to increase the grain size of the copper and to provide a grain structure that is stable over time at ambient conditions and during subsequent processing. After annealing, the average grain size of the copper is at least about 1 &mgr;m in at least one dimension. The copper that is electroplated on the dielectric layer is then removed using an expedient such as chemical mechanical polishing.

Abstract: A method for making an integrated circuit includes forming an aluminum layer adjacent a semiconductor wafer, and forming a photoresist layer adjacent the aluminum layer, with at least a portion of the aluminum layer being uncovered. The method also includes exposing the photoresist layer to a pattern image, developing the exposed photoresist layer using a developer and stripping away undeveloped photoresist portions to define a mask including mask features having reduced widths than would otherwise occur adjacent the aluminum layer. The reduced widths are based upon an interaction between the photoresist, the developer and the aluminum. The method may include etching the aluminum layer using the mask to thereby define circuit features having a smaller critical dimension than would otherwise be produced.

Abstract: A method of manufacturing an interconnection layer for a semiconductor device comprising the steps of forming a conductive pattern near a surface of a semiconductor substrate or on the surface of the semiconductor substrate, forming an insulation layer on a surface of the conductive pattern, forming grooves in the insulation layer exposing portions of the conductive pattern, forming a first barrier layer pattern on an upper surface of the insulation layer and on sidewalls and bottoms of each of the grooves, selectively forming a seed layer on portions of the first barrier layer pattern, selectively forming a copper interconnection layer on the first barrier layer pattern and the seed layer, and forming a second barrier layer on an upper surface and sides of the copper interconnection layer.

Abstract: An electronic device is formed on a chip of semiconductor material covered by a layer of insulating material. Metal interconnection elements form, on the insulating layer, connection pads to which a soldering material is applied. To permit good heat dissipation, the device has a metal plate partially incorporated in the insulating layer and having a surface which is coplanar with the pads and to which soldering material is applied. The electronic device is secured to a mounting substrate having a corresponding metal plate.

Abstract: A semiconductor device provided with a shallow metal basin having a flange outwardly extending from the top edge of the side wall of the shallow metal basin, to receive a semiconductor device chip having one or more semiconductor device elements disposed therein and one or more bonding pads arranged thereon, an insulator frame having one or more external terminals arranged thereon, the external terminals being connected with the bonding pads, and the insulator frame being arranged on the flange of the shallow metal basin, and a plastic layer molded to cover the semiconductor device chip, resultantly realizing a semiconductor device packaged in a chip scale package of which the production procedure is simplified and the heat dissipation efficiency and the integration are remarkably improved.

Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) silicon-oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium silicon-oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium silicon-oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide. However, the zirconium silicon-oxynitride gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability.

Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: A semiconductor device includes a main circuit part having a semiconductor device formed on an electrode plate of a lead frame and a control circuit part having protective functions, which is integrally molded by a resin mold part into an integral mold structure.

Abstract: A semiconductor device including a plurality of chip units each defined by a side wall and arranged in a state such that a side wall of a chip unit abuts a corresponding side wall of an adjacent chip unit, and an interconnection structure for interconnecting a plurality of terminals of a side wall of a chip unit to corresponding terminals of a side wall of an adjacent chip unit that abuts the chip unit at the respective side walls.

Abstract: A method of manufacturing a semiconductor device, which comprises a step of forming an oxide film by oxidizing a surface of semiconductor layer in an atmosphere containing an oxygen-activated species at a temperature of over 550° C. A method of manufacturing a semiconductor device, which comprises the steps of forming an oxide film by oxidizing a surface of semiconductor in an atmosphere containing an oxygen-activated species, and removing the oxide film so as to expose a surface of the semiconductor. A method of manufacturing a semiconductor device which comprises a step of feeding an oxidizing source gas comprising as a main component oxygen atomic radicals of singlet state in an excited state to a silicon layer thereby to oxidize a surface of the silicon layer, thus forming a silicon oxide film.

Abstract: A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.

Abstract: A first convex portion and a second convex portion are formed on a semiconductor substrate at a prescribed interval, an impurity diffusing region is formed on an upper portion of the semiconductor substrate placed between the first and second convex portions, and a thinned first polysilicon film is formed on the impurity diffusing region and the first and second convex portions. Thereafter, arsenic ions are implanted into the first polysilicon film to make the first polysilicon film conductive. Thereafter, a second polysilicon film having a film thickness larger than that of the first polysilicon film is formed, and phosphorus ions are implanted into the second polysilicon film to make the second polysilicon film conductive. Thereafter, a tungsten silicide film is formed on the second polysilicon film, and the tungsten silicide film and the first and second polysilicon films are patterned.

Abstract: A method for etching a doped polysilicon layer. A first doped polysilicon layer of a first conductive type and a second doped polysilicon layer of a second conductive type are formed. An etching process is performed to pattern the first doped polysilicon layer and the second doped polysilicon layer. The etching process includes a first main etching step and a second main etching step. The etching pressure of the first main etching step is lower than the etching pressure of the second main etching step.

Abstract: A method of planarizing a layer of dielectric material is disclosed herein that is particularly suitable for planarizing inter-layer-dielectrics (ILD) or inter-metal-dielectrics (IMD). The planarizing method comprises the steps of depositing a layer of sacrificial oxide over the dielectric material, depositing a layer of amorphous silicon over the sacrificial oxide layer by either sputtering or plasma enhanced chemical vapor deposition (PECVD) at a temperature less than about 500 degrees Celsius, performing a first chemical-mechanical polishing of the amorphous silicon layer to form a self-aligned mask for a subsequent etching step, etching a portion of the sacrificial oxide layer to form a channel therein, and performing a second chemical-mechanical polishing to remove the remaining amorphous silicon layer and the remaining sacrificial oxide, and to substantially planarize the underlying dielectric material.

Abstract: The present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another embodiment, the trench is filled with gettering material 72 such as polysilicon. The two gettering mechanisms may be combined 82,84. The invention is useful for providing gettering in bonded wafers and in silicon-on-insulator devices (FIGS. 4,5).

Abstract: After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.

Abstract: An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source.

Abstract: A method of forming a gate electrode with a titanium polycide structure which can prevent abnormal oxidation of the gate electrode and reduce the resistivity of the gate electrode when performing a re-oxidation process, is disclosed. According to the present invention, a gate oxide layer, a polysilicon layer and a titanium silicide layer are formed on a semiconductor substrate, in sequence. A mask insulating layer is then formed in the shape of a gate electrode on the titanium silicide layer and the titanium silicide layer and the polysilicon layer are etched using the mask insulating layer to form a gate electrode. Thereafter, the substrate is oxidized using re-oxidation process to form an oxide layer with a uniform thickness on the side wall of the gate electrode and on the surface of the substrate. Here, the re-oxidation process is performed at the temperature of 750° C. or less using dry oxidation. Furthermore, the re-oxidation process is performed at the temperature of 700 to 750° C.

Abstract: A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by etching a portion of the ends of the layer of tunnel oxide forming cavities, forming silicon nitride plugs in the cavities and forming a layer of oxide on the surface of the flash memory device wherein the silicon nitride plugs minimize gate edge lifting.

Abstract: A circuit protects against electrostatic discharge and includes a pad which receives an external signal source. The transistor of the present invention is connected to the circuit to be protected and includes a semiconductor body of a first conductivity type and serves as the collector of the transistor and is connected to the pad. A first doped region of a second conductivity type is contained in the semiconductor body and serves as the base of the transistor and forms a collector-to-base junction surface with the semiconductor body. A second doped region of the first conductivity type is contained in the first doped region and serves as the emitter of the transistor and forms a base-to-emitter junction surface with the first doped region. The first and second doped regions are electrically connected for establishing a shorted connection between the base and emitter.