Abstract: An analog-digital conversion apparatus may include a control unit configured for receiving an analog-digital (AD) conversion request from a plurality of processing modules; and an analog-digital converter (ADC) configured for performing analog-digital conversion according to the AD conversion request received from the control unit, in which the control unit is configured to integrate the AD conversion request according to periodicity of the AD conversion request and to transfer the integrated AD conversion request to the ADC.

Abstract: A pipelined ADC that does not wait for the residue of a signal to settle to be delivered to the next stage of the pipeline, and thus passes signals to subsequent stages at faster than conventional speeds. A pipelined ADC is used that processes signals representing the boundaries of the search space. Thus, each stage does not necessarily receive the signal as pre-processed by the prior stage, but rather the search space boundaries as pre-processed by the prior stage. Reducing the “search space” of the ADC is equivalent to creating the residues in each step of a pipeline as in the prior art. An ADC operating in this fashion operates without error even if the residual search space boundary outputs from one state are presented to the next stage before the outputs have settled, and can run faster for a given power and bandwidth.

Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.

Abstract: An analog-to-digital converter (ADC) is based on single-bit delta-sigma quantization. The ADC includes an integrator, a threshold detector, a feedback block, a range control circuit and an output processing block. The ADC is configured to, based on its own generated digital bitstream, adjust the magnitude of a subtrahend signal in order to achieve autonomous auto-ranging of the ADC during the integration time of a measurement. In particular, the auto-ranging allows for the efficient conversion of an analog input signal with high dynamic range, for example ambient light, to a digital output signal.

Abstract: An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2L reference times corresponding to 2L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

Abstract: An antenna assembly and an electronic device are disclosed. The antenna assembly includes a near-field-communication (NFC) integrated-circuit (IC), a conductive loop, and a radiation-field enhancer. The NFC IC includes a first differential signal port and a second differential signal port for providing a differential excitation current. The first metal stub extends from the first ground portion of the ground plane and electrically connected to the first differential signal port. The conductor is spaced apart from the ground plane, and is electrically connected to the second differential signal port and the second ground portion, respectively. The radiation-field enhancer is disposed between the conductor and the ground plane and configured to enhance a field strength of an NFC radiation-field generated by the conductor in response to the differential excitation current being transmitted.

Abstract: Single band and multiband wireless antennas are an important element of wireless systems. Competing tradeoffs of overall footprint, performance aspects such as impedance matching and cost require not only consideration but become significant when multiple antenna elements are employed within a single antenna such as to obtain circular polarization transmit and/or receive. Accordingly, it would be beneficial to provide designers of a wide range of electrical devices and systems with compact single or multiple frequency band antennas which, in addition to providing the controlled radiation pattern and circular polarization purity (where required) are impedance matched without substantially increasing the footprint of the antenna and/or the complexity of the microwave/RF circuit interfaced to them, whilst supporting multiple signals to/from multiple antenna elements in antennas employing them.

Abstract: A wide bandwidth ADC circuit that combines a resistive-input continuous-time sigma-delta ADC circuit with a second ADC circuit having a switched capacitor input. The combination of these two ADC circuits can achieve an easy-to-drive, alias free, wide bandwidth ADC that has excellent DC precision.

Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.

Abstract: In accordance with an embodiment, a circuit includes a current digital-to-analog converter (DAC) having a current switching network coupled to a current DAC output, a first cascode current source coupled between a first supply node and the current switching network, a second cascode current source between a second supply node and the current switching network, and a shorting switch coupled between a first cascode node of the first cascode current source, and a second cascode node of the second cascode current source.

Abstract: A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-to-time converter. Further, the method includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adjusting a first entry of a look-up table based on the measured temporal order.

Abstract: A method of enhancing SAR ADC conversion rate by employing a new value shifted capacitor DAC. The value shifted capacitor DAC decreases largest capacitor to improve the reference voltage settling. The reduction of capacitor is added back onto the smaller capacitor DAC to maintain the same total capacitor value. The binary search outputs are re-combined and processed to produce final binary ADC outputs. The overhead of using value shifted capacitor DAC is the extra latency needed for re-combined logic.

Abstract: Embodiments include applying neural network technologies to encoding/decoding technologies by training and encoder model and a decoder model using a neural network. Neural network training is used to tune a neural network parameter for the encoder model and a neural network parameter for the decoder model that approximates an objective function. The common objective function may specify a minimized reconstruction error to be achieved by the encoder model and the decoder model when reconstructing (encoding then decoding) training data. The common objective function also specifies for the encoder and decoder models, a variable f representing static aspects of the training data and a set of variables z1:T representing dynamic aspects of the training data. During runtime, the trained encoder and decoder models are implemented by encoder and decoder machines to encode and decoder runtime sequences having a higher compression rate and a lower reconstruction error than in prior approaches.

Abstract: A two-dimensional square constraint encoding and decoding method and device, relating to the fields of data storage and data communication. The encoding method includes caching a one-dimensional data stream, and dividing the one-dimensional data stream into several sets of one-dimensional 2-bit data; according to an encoding table, encoding each set of 2-bit data into a 3*2 two-dimensional codeword in sequence by an encoder, and then cascading all the two-dimensional codewords into a two-dimensional constraint array in a specified order; the decoding method includes reading the two-dimensional constraint array by a decoder, and dividing the two-dimensional constraint array into several 3*2 two-dimensional codewords; decoding each two-dimensional codeword into the one-dimensional 2-bit data in sequence through a decoding table, and then successively assembling the generated one-dimensional 2-bit data into the one-dimensional data stream and outputting.

Abstract: An apparatus and associated method are provided involving a housing having a periphery configured to operate as a second antenna, a third antenna, and a fourth antenna. The periphery includes a top wall having a first slot formed therein, a first side wall having a second slot formed therein, and a second side wall having a third slot formed therein. The top wall is arranged between the first side wall and the second side wall, and a top portion of the periphery is defined between the second slot and the third slot. The top portion is divided into a first top side portion and a second top side portion via the first slot. Further, the first top side portion operates as the second antenna, and the second top side portion operates as both the third antenna and the fourth antenna.

Abstract: A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.

Abstract: An analog-to-digital (ADC) circuit is disclosed that includes a first stage, a first amplifier, and a second amplifier. The first stage includes signal processing circuitry, and is configured to receive a differential input signal and generate a differential residue voltage signal on differential output nodes of the first stage. The first amplifier includes first amplifier circuitry. The first amplifier is electrically connected to the differential output nodes of the first stage, and configured to receive the differential residue voltage signal, and generate a first differential voltage signal from the differential residue voltage signal. The second amplifier includes second amplifier circuitry. The second amplifier is electrically connected to differential output nodes of the first amplifier, and configured to receive the first differential voltage signal, and generate a second differential voltage signal from the first differential voltage signal.

Abstract: In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

Abstract: A digital-to-analog converter (DAC) system preferably includes one or more optical modulators and can optionally include one or more electronic DAC arrays. A method for digital-to analog conversion preferably includes receiving digital inputs and providing analog optical outputs. The method for digital-to analog conversion is preferably performed using the DAC system.

Abstract: Methods and systems are provided for decoding variable-length codes in a parallel process. A stream of variable-length code words is divided into fixed length words. A plurality of parallel sets of decoder circuits each receive, in parallel, a current fixed length word and a prior fixed length word. Each decoder circuit has a respective fixed leftover bit-count. Each decoder circuit generates a respective output that may include a decoded symbol and a new leftover bit-count. Each respective output is determined based on the respective current fixed length word, the respective prior fixed length word, and the respective fixed leftover bit-count. A set of selected decoder circuit outputs is generated for each set of the parallel sets of decoder circuits based on a set of first leftover bit-counts. One output from each set of selected decoder circuit outputs is selected as a final output based on a second prior leftover bit-count.