Abstract: Embodiments include applying neural network technologies to encoding/decoding technologies by training and encoder model and a decoder model using a neural network. Neural network training is used to tune a neural network parameter for the encoder model and a neural network parameter for the decoder model that approximates an objective function. The common objective function may specify a minimized reconstruction error to be achieved by the encoder model and the decoder model when reconstructing (encoding then decoding) training data. The common objective function also specifies for the encoder and decoder models, a variable f representing static aspects of the training data and a set of variables z1:T representing dynamic aspects of the training data. During runtime, the trained encoder and decoder models are implemented by encoder and decoder machines to encode and decoder runtime sequences having a higher compression rate and a lower reconstruction error than in prior approaches.

Abstract: Receiver circuitry to convert a pulse-width-modulated (PWM) signal into a digital data signal includes analog-to-digital converter circuitry that converts the PWM signal into an intermediate signal, a timing generator that derives control signals from the intermediate signal, analog charge storage circuitry that is charged and discharged according to the control signals, and circuitry that derives a digital output signal from an analog waveform output by the charge storage circuitry. The charge storage circuitry includes a capacitance and a current-limiting element, one of which is variable to control a time constant of the charge storage circuitry for calibration to a data rate of the PWM signal. A control signal may be single-ended and compared to a threshold, or may be differential with the legs compared to each other. The output is derived on a falling clock edge, and maintained until a subsequent falling clock edge.

Abstract: A technique to prevent a retrieving process of a conversion rule from taking a longer time is provided.

Abstract: An antenna including a ground plane, a metal plate arranged facing the ground plane, and a supply wire for connecting the plate to a generator or a receiver, such that the antenna has a first resonance frequency in a patch antenna mode. The antenna further includes a ground wire connecting the plate to the ground plane, and a capacitive element arranged in series with the ground wire between the supply wire and the ground plane, such that the antenna also has a second resonance frequency in a wire-plate antenna mode.

Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc.

Abstract: Systems, apparatuses, and methods for implementing an anti-aliasing technique for a time-to-digital converter are described. A pulse generator generates a pulse with a width that is representative of a voltage level of a supply voltage. A buffer chain receives the pulse from the pulse generator. A first sum is calculated by adding together a number of one bits in a first portion of the buffer chain. Also, a second sum is calculated by adding together a number of one bits in a second portion of the buffer chain. Then, a third sum is calculated by adding the first sum to the second sum if the first sum is saturated. Otherwise, the third sum is equal to the first sum if the first sum is not saturated. The third sum is used as a representation of the voltage level of the supply voltage.

Abstract: Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, nth order resonant bandpass filtering with n>1, and signal sub-sampling in an ith Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using nth order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

Abstract: An analog-to-digital converter (ADC) with split-gate laddered-inverter quantizer is presented herein. The ADC converts, via the split-gate laddered-inverter quantizer, an analog input voltage into a digital output value. The split-gate laddered-inverter quantizer separately couples, during respective phases of a clock signal via respective capacitances, a reference voltage and an input voltage corresponding to the analog input voltage to P-type metal-oxide-semiconductor (PMOS) gates of a PMOS branch of the split-gate laddered-inverter quantizer and N-type metal-oxide-semiconductor (NMOS) gates of an NMOS branch of the split-gate laddered-inverter quantizer to optimize current flow at respective frequencies. Further, the split-gate laddered-inverter quantizer separately biases, during the respective phases of the clock signal, the NMOS gates and the PMOS gates at respective bias voltages to optimize the current flow at the respective frequencies.

Abstract: An antenna structure includes a first antenna, a second antenna, a third antenna, and a first grounding portion. The first antenna and the second antenna operate at a first frequency. The first antenna is disposed side by side with the second antenna, and the first antenna and the second antenna are orthogonally polarized. The third antenna operates at a second frequency, and the second frequency is lower than the first frequency. The first grounding portion includes a first side edge and a second side edge opposite to each other. The first antenna and the second antenna are connected to the first side edge and the third antenna is connected to the second side edge. An electronic device includes the said antenna structure.

Abstract: An electronic device is provided. The electronic device includes a metal housing, an insulation element, and an antenna unit. The insulation element is disposed on the metal housing and includes a first heat dissipation hole. The antenna unit is disposed on the insulation element and includes a radiation portion and a feeding portion. The radiation portion is composed of a conductor. The feeding portion is electrically connected to the radiation portion and a grounding plane. In this way, according to the electronic device, space configuration inside the electronic device is saved and a shielding effect of the metal housing is prevented from affecting stability of sending and receiving a signal.

Abstract: Aspects described herein relate to at least a portion of a connector configured to support wireless communications that includes multiple chambers, each at least partially enclosed by a continuous isolation structure to provide electrical signal isolation and defining an inner surface. At least one terminal in a first chamber of the multiple chambers is configured for a first interface, and at least one terminal in a second chamber of the multiple chambers is configured for a second interface.

Abstract: An antenna device includes a substrate extending within a substrate plane, the substrate having a first side and an oppositely arranged second side, and a three-dimensional shape structure which is arranged on the first side and protrudes from the substrate plane, and a strip structure arranged at the three-dimensional shape structure, and a rear-side metallization which is arranged on the second side of the substrate and is electrically coupled to the strip structure so that the strip structure and the rear-side metallization form a loop antenna.

Abstract: An antenna-integrated radio frequency (RF) module includes a multilayer substrate disposed between an integrated chip (IC) and patch antennas, signal vias, and ground members. The IC is configured to generate RF signals. The signal vias are configured to connect and transmit/receive the RF signals from each of the patch antennas to the IC. The ground members are disposed on an outer surface layer and intermediate surface layers of the multilayer substrate to surround each of the patch antennas and the signal vias.

Abstract: An antenna apparatus includes a ground plane; a first patch antenna pattern having a first bandwidth and spaced apart from the ground plane; a second patch antenna pattern spaced apart from the ground plane and the first patch antenna and overlapping at least a portion of the first patch antenna pattern; and guide vias disposed between the first patch antenna pattern and the ground plane and electrically connecting the first patch antenna pattern to the ground plane. The second patch antenna pattern has a second bandwidth corresponding a frequency higher than a frequency of the first bandwidth. The guide vias are disposed along a first side of the first patch antenna pattern.

Abstract: Implementations for heat structure for thermal mitigation are described. The described heat structures, for instance, provide a multi-layered structure that optimizes heat spreading and dissipation, as well as wireless performance of wireless devices. A heat structure, for instance, is installed internally in a wireless device adjacent various internal components to absorb heat generated by the components, and to dissipate the heat. According to various implementations, a heat structure is implemented as a thermally conductive layer surrounded by layers of electrically conductive material. Electrically conductive vias can be formed that traverse the thermally conductive layer and form an electrical connection between different electrically conductive layers to mitigate current flow in the thermally conductive layer.

Abstract: This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (SIN) and outputs a time-encoded output signal (SOUT). A filter arrangement receives the input signal and also a feedback signal (SFB) from the TEM output, and generates a filtered signal (SFIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (SPWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance is coupled to a signal path for the feedback signal to provide a passive filter.

Abstract: This antenna includes: a ground plane; a capacitive roof, parallel with the ground plane; a supply probe, which is electrically isolated from the ground plane and runs between the ground plane and the capacitive roof so as to supply the capacitive roof with electricity, the supply probe being intended to be connected to a transmission line; a set of shorting wires, which are arranged in parallel around the supply probe such that each shorting wire electrically connects the capacitive roof to the ground plane, each shorting wire being coated with a magneto-dielectric material.

Abstract: A data compressor a zero-value remover, a zero bit mask generator, a non-zero values packer, and a row-pointer generator. The zero-value remover receives 2N bit streams of values and outputs 2N non-zero-value bit streams having zero values removed from each respective bit stream. The zero bit mask generator receives the 2N bit streams of values and generates a zero bit mask for a predetermined number of values of each bit stream in which each zero bit mask indicates a location of a zero value in the predetermined number of values corresponding to the zero bit mask. The non-zero values packer receives the 2N non-zero-value bit streams and forms a group of packed non-zero values. The row-pointer generator that generates a row-pointer for each group of packed non-zero values.

Abstract: The present disclosure provides an antenna feeder assembly of a multi-band antenna, comprising a first feeder supporting propagation of waves in a first frequency band and a second feeder supporting propagation of waves in a second frequency band lower than the first frequency band. The second feeder coaxially surrounds the first feeder. The first feeder comprises a dielectric emitting section and a dielectric radiating section; wherein each of the dielectric emitting section and the radiating section includes an inner cavity, a wall, and sub-wavelength elements on an external surface of the wall. The present disclosure also provides a multi-band microwave antenna, comprising a dish reflector, a subreflector, and the above-mentioned antenna feeder assembly.

Abstract: Facilitating energy-efficient wireless communications for advanced networks (e.g., 4G, 5G, and beyond) with low-resolution digital-to-analog converters is provided herein. Operations of a system can comprise determining first values. Respective values of the first values can be digital samples of transmission and reception chains determined based on symbols transformed from bits. The operations can also comprise facilitating a quantization of the first values resulting in second values. Facilitating the quantization can be based on a cost function associated with processing the first values. Further, the operations can comprise outputting the second values as a continuous time signal over antennas of a base station device. The second values can comprise fewer values than the first values.