Abstract: A communication device for wireless communication includes a housing having a front dielectric cover, a back dielectric cover, a metal frame circumferentially arranged between the front dielectric cover and the back dielectric cover, and an aperture. The metal frame forms a first antenna that is configured to radiate in a first set of frequency bands. The communication device further includes a circuit arranged inside the housing. The circuit is electrically isolated from the metal frame and includes at least one first feed line coupled to the metal frame and configured to feed the first antenna with a first set of radio frequency signals in the first set of frequency bands. The communication device further includes a second antenna arranged inside the housing and configured to radiate in a second frequency band non-overlapping with the first frequency band.

Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.

Abstract: During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

Abstract: Disclosed are a data compression method, a computer-readable storage medium, and an electronic device. The method includes: converting each data in a to-be-compressed data set into binary data in a preset format; determining a to-be-compressed bit and a significant bit for the each data in the to-be-compressed data set based on a sequence of all bits of the binary data; determining a compression bit width corresponding to the to-be-compressed data set based on bit widths of the significant bits; compressing the each data in the to-be-compressed data set based on the compression bit width, to obtain a compressed data set; and generating attribute information of the compressed data set. According to the present disclosure, the significant bit can be determined based on the sequence of all bits without adjusting orders of the bits of the binary data, thereby simplifying a data compression process and improving efficiency of data compression.

Abstract: A neural network deep learning data control apparatus includes: a memory; an encoding circuit configured to receive a data sequence, generate a compressed data sequence in which consecutive invalid bits in a bit string of the data sequence are compressed into a single bit of the compressed data sequence, generate a validity determination sequence indicating a valid bit and an invalid bit in a bit string of the compressed data sequence, and write the compressed data sequence and the validity determination sequence to the memory; and a decoding circuit configured to read the compressed data sequence and the validity determination sequence from the memory, and determine a bit in the bit string of the compressed data sequence set for transmission to a neural network circuit, based on the validity determination sequence, such that the neural network circuit omits an operation with respect to non-consecutive invalid bits.

Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

Abstract: Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

Abstract: A current source and/or current sink digital-to-analog converter (DAC) includes a DAC circuit that converts a digital code to an analog current or voltage signal, an optional transconductance circuit that converts a voltage output of the DAC circuit into a current signal, and an output circuit that amplifies a current output of the DAC circuit or optionally amplifies a current output of the transconductance circuit to set a desired high current output for application to an output of the current source and/or current sink DAC. A power supply control current may be coupled to a power supply circuit that supplies power to the output circuit of the current source and/or current sink DAC. The power supply control current adjusts the output of the power supply circuit to cause the current source and/or current sink DAC to operate at a higher power efficiency.

Abstract: A memory system includes a storage device and a memory controller. The memory controller includes an encoder and a decoder. The encoder includes a first code table updating section configured to update the encoding code table and an encoding flow controlling section configured to control input to the first code table updating section by using a first data amount indicating a data amount of the input symbol. The first data amount is calculated based on the input symbol. The decoder includes a second code table updating section configured to update the decoding code table and a decoding flow controlling section configured to control input to the second code table updating section by using a second data amount indicating a data amount of the output symbol. The second data amount is calculated based on the output symbol in the same way as the calculation of the first data amount.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for content recommendation using neural networks. In One aspect, a method includes: receiving context information for an action recommendation from multiple possible actions; processing the context information using a neural network that includes Bayesian neural network layers to generate, for each of the actions, one or more parameters of a distribution over possible action scores for the action, where each parameter for each Bayesian layer is associated with data representing a probability distribution over multiple possible current values for the parameter; for each parameter of each Bayesian neural network layer, selecting the current value for the parameter using data representing probability distribution over possible current values for the parameter; and selecting an action from multiple possible actions using the parameters of the distributions over the possible action scores for the action.

Abstract: New and efficient protocols are provided for privacy-preserving machine learning training (e.g., for linear regression, logistic regression and neural network using the stochastic gradient descent method). A protocols can use the two-server model, where data owners distribute their private data among two non-colluding servers, which train various models on the joint data using secure two-party computation (2PC). New techniques support secure arithmetic operations on shared decimal numbers, and propose MPC-friendly alternatives to non-linear functions, such as sigmoid and softmax.

Abstract: Fast, efficient, and robust compression-based methods for detecting boundaries in arbitrary datasets, including sequences (1D datasets), are desired. The methods, each employing three simple algorithms, approximate the information distance between two adjacent sliding windows within a dataset. One of the algorithms calculates an initial ordered list of subsequences; while a second algorithm updates the ordered list of subsequences by dropping a first entry and appending a last entry rather than calculating completely new ordered lists with each iteration. Large values in the distance metric are indicative of boundary locations. A smoothed z-score or a wavelet-based algorithm may then be used to locate peaks in the distance metric, thereby identifying boundary locations. An adaptive version of the method employs a collection of window sizes and corresponding weighting functions, making it more amenable to real datasets with unknown, complex, and changing structures.

Abstract: An Analog-to-Digital Converter (ADC) includes a plurality of ADC channels connected to an in-service signal input via an isolated power combiner; an on-chip circuit including a calibration source connected to the isolated power combiner; and one or more switches configured to switch the ADC between an in-service mode and a calibration mode. The one or more switches are set such that, in the calibration mode, the in-service signal input is disconnected and the on-chip circuit is connected to the isolated power combiner, and, in the in-service mode, the in-service signal input is connected and the on-chip circuit is disconnected to the isolated power combiner. In the calibration mode, the on-chip circuit is configured to provide a test signal to the plurality of ADC channels for a determination of interleave errors in the plurality of ADC channels.

Abstract: Systems and methods for lossless compression of tabular numeric data are provided. The system can include one or more data compression servers executing data compression system code to compress the tabular numeric data, a storage database to store the compressed tabular numeric data, and one or more data decompression servers to decompress the tabular numeric data for use. The one or more data compression servers, the storage database, and the one or more data decompression servers can communicate via a communication network. The system can receive the uncompressed tabular numeric data from one or more data generation systems, processes the uncompressed tabular numeric data with the data compression system code, and generate a compressed table of numeric information, which can be stored in the database, or later decompressed by the one or more data decompression servers.

Abstract: An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.

Abstract: Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

Abstract: To reduce the effect on the communication performance of an antenna to secure a good communication state with respect to the antenna. An acoustic output device includes a speaker for outputting sound, a cell having one surface facing in a facing direction represented by a predetermined direction, a control board for controlling predetermined parts, and an antenna for sending and receiving signals, the antenna having at least a portion spaced from the control board and the cell. The cell and the control board are positioned side by side with each other in directions different from thicknesswise directions of the control board. The facing direction is different from the directions in which the cell and the control board are side by side with each other. The antenna is positioned side by side with at least one of the control board or the cell in the thicknesswise directions or the facing direction.

Abstract: An isolator of embodiments includes a ?? analog-digital converter configured to convert an analog signal into a digital signal of one bit and transmit the digital signal of one bit as normal data, a time direction multiplexing circuit configured to perform time direction multiplexing of alternately performing conversion of the normal data into a digital differential signal and transmission of the digital differential signal, and transmission of a special signal different from the normal data, and an insulated transmission circuit configured to transmit the digital differential signal and the special signal transmitted from the time direction multiplexing circuit via an insulating layer.

Abstract: A radio frequency module includes a first substrate having a first principal surface and a second principal surface on the opposite side to the first principal surface; a signal terminal which is provided on the first principal surface and through which a signal is transmitted to and received from an external circuit; a power supply terminal that is provided on the second principal surface and is supplied with a power supply signal; an antenna; and a radio frequency electronic component that is electrically connected to the signal terminal, the power supply terminal and the antenna, and controls transmission and reception of the antenna based on the signal and the power supply signal.

Abstract: A non-uniform sampling pADC is disclosed. The pADC may include an optical pulse source configured to generate uniform optic pulses. The pADC may include a non-uniform sampling system. The non-uniform sampling system may include an inter-pulse timing modulation sub-system configured to convert the uniform optic pulses into non-uniform optic pulses. The non-uniform sampling system may include a timing control sub-system configured to control the timing of the optical pulse source. The pADC may include an optical modulator configured to modulate the non-uniform optical pulses. The pADC may include a photodetector configured to convert the modulated non-uniform optic pulses into electronic pulses. The pADC may include a pulse capture assembly configured to capture a pulse amplitude of the electronic pulses and generate sampled radio frequency output pulses. The pADC may include a quantizer configured to quantize the sampled radio frequency output pulses and generate digital radio frequency output signals.