Patents Examined by Jean B. Jeanglaude
  • Patent number: 10491237
    Abstract: A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: November 26, 2019
    Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Chulwoo Kim, Chaekang Lim
  • Patent number: 10491234
    Abstract: A system includes a central processing unit (CPU) core, and a pulse width modulator (PWM) controller configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC), an accumulator, a sum register, and an oversampling register set. The oversampling register set is configurable by the CPU core to specify time points during each PWM cycle when the ADC is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator accumulates digital samples from the ADC and stores an accumulated sum in the sum register. The CPU core reads the accumulated sum from the sum register, and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: November 26, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manish Bhardwaj, Devin Allen Cottier, David Peter Foley
  • Patent number: 10491229
    Abstract: The application provides a vector quantization digital-to-analog conversion circuit, applied to an oversampling converter, characterized that the vector quantization digital-to-analog conversion circuit includes a vector quantization circuit, configured to generate a vector quantization signal, a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: November 26, 2019
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventor: Wen-Chi Wang
  • Patent number: 10468754
    Abstract: The present technology relates to a multiband antenna for wireless mobile communication devices such as cellular telephones. The antenna may include a bifurcated ring structure along one, two, three or all four edges of the device. The ring structure may include bifurcated metal conductors, or bars, extending along the length of the one or more edges.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 5, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventor: Kiran Vanjani
  • Patent number: 10461866
    Abstract: In a modulation system that modulates and transmits an optical signal over at least one optical fiber in response to an input digital data word of N bits, there is an input enabled for receiving the digital data word; an electrically controllable modulator having one or more waveguide branches, where each branch receives an input of an unmodulated optical signal; and a digital to digital converter enabled for converting the N bits to a digital drive vector corresponding to M drive voltage values, where M>N and N>1. The electrically controllable modulator couples the drive voltage values to the unmodulated optical signal(s). The coupling enables pulse modulation of the unmodulated optical signal(s) thereby generating pulse modulated optical signal(s). The electrically controllable modulator outputs the pulse modulated optical signal(s) to one or more outputs that are enabled for transmitting the pulse modulated optical signal(s) over at least one optical fiber.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: October 29, 2019
    Assignee: Ramot at Tel-Aviv University Ltd.
    Inventors: Yossef Ehrlichman, Ofer Amrani, Shlomo Ruschin
  • Patent number: 10461761
    Abstract: An analog-to-digital converter (ADC) is disclosed. The ADC includes a successive approximation register and a voltage-to-time conversion element. The successive approximation register is configured to receive an input signal and to generate a first digital signal and a residue voltage. The voltage-to-time conversion element is configured to convert the residue voltage to a time domain representation. The voltage-to-time conversion element includes an amplifier having an input coupled to an output of the successive approximation register and configured to receive the residue voltage, and a zero crossing detector directly coupled to an output of the amplifier. A time-to-digital converter is coupled to an output of the zero crossing detector and is configured to generate a second digital signal.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Martin Kinyua
  • Patent number: 10454160
    Abstract: There is provided an antenna device configured to be shaped as a sheet. The antenna device includes an antenna portion provided on one surface of the sheet and configured to implement at least one of transmission of a transmission wave and reception of a reflected wave from a target, and an absorption unit provided on the other surface of the sheet and configured to absorb spurious.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 22, 2019
    Assignee: DENSO TEN Limited
    Inventor: Takahiro Shinojima
  • Patent number: 10454492
    Abstract: A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 22, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Akira Shikata, Junhua Shen, Anping Liu
  • Patent number: 10447292
    Abstract: Multiple-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multiple-bit parallel SAR ADC circuit includes a number of SAR controller circuits, each of which includes SAR register circuits. Each SAR register circuit receives and stores a corresponding digital bit that is based on a comparison of an analog input signal and a corresponding digital-to-analog converter (DAC) analog signal. Each SAR register circuit also provides a corresponding digital signal based on the digital bit. A DAC circuit receives a reference voltage, and uses the reference voltage and a subset of digital signals generated by SAR controller circuits to generate multiple DAC analog signals. A compare circuit generates the digital bit corresponding to each SAR controller circuit, wherein a number of the digital bits are generated in parallel. Each digital bit collectively forms a digital representation of the analog input signal.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 15, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Burt Lee Price
  • Patent number: 10448538
    Abstract: The disclosed wireless router may include (i) an enclosure, (ii) an antenna, (iii) a printed circuit board assembly, (iv) a radiative heat sink disposed between the antenna and the printed circuit board assembly within the wireless router such that the radiative heat sink is configured to shield the antenna from spurious emissions generated by the printed circuit board assembly, and (v) a fan disposed at a center of the radiative heat sink such that the fan is configured to cool the wireless router by circulating air within the enclosure rather than pushing air through venting in the enclosure. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: December 10, 2017
    Date of Patent: October 15, 2019
    Assignee: Symantec Corporation
    Inventors: Christopher Gaul, Michel Billard, Paul Roybal
  • Patent number: 10424969
    Abstract: An electrically conductive material configured having at least one opening of various unlimited geometries extending through its thickness is provided. The opening is designed to modify eddy currents that form within the surface of the material from interaction with magnetic fields that allow for wireless energy transfer therethrough. The opening may be configured as a cut-out, a slit or combination thereof that extends through the thickness of the electrically conductive material. The electrically conductive material is configured with the cut-out and/or slit pattern positioned adjacent to an antenna configured to receive or transmit electrical energy wirelessly through near-field magnetic coupling (NFMC). A magnetic field shielding material, such as a ferrite, may also be positioned adjacent to the antenna. Such magnetic shielding materials may be used to strategically block eddy currents from electrical components and circuitry located within a device.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: September 24, 2019
    Assignee: NuCurrent, Inc.
    Inventors: Alberto Peralta, Md. Nazmul Alam, Vinit Singh, Sina Haji Alizad
  • Patent number: 10419036
    Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 17, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Viswanathan Nagarajan, Srinivas Kumar Reddy Naru, Narasimhan Rajagopal
  • Patent number: 10419021
    Abstract: The transmission of broadcast data, such as financial data and news feeds, is accelerated over a communication channel using data compression and decompression to provide secure transmission and transparent multiplication of communication bandwidth, as well as reduce the latency. Broadcast data may include packets having fields. Encoders associated with particular fields may be selected to compress those particular fields.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 17, 2019
    Assignee: Realtime Data, LLC
    Inventors: James J. Fallon, Paul F. Pickel, Stephen J. McErlain, Carlton J. Melone, II
  • Patent number: 10419016
    Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 17, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jinda Yang, Liren Zhou
  • Patent number: 10419013
    Abstract: An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; delay units and a processor that is configured to generate an output digital signal that represents the input analog signal based on selected edges of the PWM pulses and delayed PWM pulses.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 17, 2019
    Assignee: ANALOG VALUE LTD.
    Inventors: Vladimir Koifman, Tiberiu Galambos, Anatoli Mordakhay
  • Patent number: 10404268
    Abstract: Method and apparatus for nonlinear signal processing include mitigation of outlier noise in the process of analog-to-digital conversion and adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. Methods, processes and apparatus for real-time measuring and analysis of variables include statistical analysis and generic measurement systems and processes which are not specially adapted for any specific variables, or to one particular environment. Methods and corresponding apparatus for mitigation of electromagnetic interference, for improving properties of electronic devices, and for improving and/or enabling coexistence of a plurality of electronic devices include post-processing analysis of measured variables and post-processing statistical analysis.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: September 3, 2019
    Inventor: Alexei V. Nikitin
  • Patent number: 10401798
    Abstract: A time-to-digital converter includes a clock signal generation circuit that generates a first cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the clock frequency of a reference clock signal and further generates a first clock signal based on a first signal and the first cycle signal, a clock signal generation circuit that generates a second cycle signal having a voltage level that monotonously increases or decreases in a cycle corresponding to the clock frequency of a reference clock signal and further generates a second clock signal based on a second signal and the second cycle signal, and a processing circuit that converts a time difference between the transition timing of the first signal and the transition timing of the second signal into a digital value based on the first and second clock signals.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 3, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Yasuhiro Sudo, Hideo Haneda
  • Patent number: 10396432
    Abstract: An antenna-integrated radio frequency (RF) module includes a multilayer substrate disposed between an integrated chip (IC) and patch antennas, signal vias, and ground members. The IC is configured to generate RF signals. The signal vias are configured to connect and transmit/receive the RF signals from each of the patch antennas to the IC. The ground members are disposed on an outer surface layer and intermediate surface layers of the multilayer substrate to surround each of the patch antennas and the signal vias.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hong In Kim, Thomas A Kim, Ho Kyung Kang
  • Patent number: 10396814
    Abstract: A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jafar Sadique Kaviladath, Neeraj Shrivastava
  • Patent number: 10367520
    Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann