Abstract: A driving circuit is provided by the invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between an operation voltage and a power supply terminal of the first buffer for controlling a power-supplying time of the first buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter.

Abstract: Provided is a voltage level shift circuit including: a first voltage level shift circuit formed of a P-channel enhancement type transistor (M1) and an N-channel depletion type MOS transistor (M3); and a second voltage level shift circuit formed of a P-channel enhancement type transistor (M2) and an N-channel depletion type MOS transistor (M4). In the voltage level shift circuit, a cascode circuit using an N-channel depletion type transistor (M5) is serially connected to the first voltage level shift circuit, a cascode circuit using an N-channel depletion type transistor (M6) is serially connected to the second voltage level shift circuit, and a unit for complementarily controlling bias voltages of the respective cascode circuits. As a result, an output signal of the voltage level shift circuit connected to an input of a differential amplifier circuit, for expanding an input voltage range of a signal, is not affected by fluctuations in power supply voltage.

Abstract: A method for waking up a circuit, comprising charging a voltage line of the circuit with a constant wake-up current until the voltage line reaches a predetermined voltage. Also, an apparatus, comprising a circuit portion, a switch configured to selectively couple an input of the circuit portion to a supply voltage, a current source configured to generate a first current, and a control circuit configured to control a state of the switch depending on the first current.

Abstract: Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.

Abstract: Provided is a filter used for an equalizer, the filter including: a first low-pass filter unit receives an input signal and performs low frequency band filtering on the input signal; and an equalization unit that receives an output signal from the first low-pass filter unit. The equalization unit may comprise a plurality of serially connected biquad low-pass filter units, and may control a value of a capacitor that is used to control a group delay value that is generated during equalization. Thus, the filter can compensate for group delay without including a separate all pass filter, thereby reducing surface area and power consumption.

Abstract: A trim fuse circuit includes a metal fuse, a trim pad coupled to the first end of the metal fuse, a first transistor coupled to the first end of the metal fuse, a second transistor coupled to the second end of the metal fuse, an inverter coupled to the second end of the metal fuse, a switch coupled to the second end of the metal fuse, and a common trim pad coupled to the control end of the switch. The inverter outputs a data signal according to the status of the metal fuse. The trim pad can be disposed on the scribe line of a wafer. When the trim pad is cut and accordingly connects to the substrate of the wafer, the data signal is not affected.

Abstract: Compensation for an RF detector includes components having different order temperature functions. The components are combined and may be adjusted by various numbers of user-accessible terminals to provide individual adjustment for factors such as operating frequency. In some embodiments, first and second-order temperature functions are generated independently and combined to provide a polynomial function of temperature with coefficients that may be adjusted. In other embodiments, the outputs of the function generators may be more complex functions of temperature with various adjustable parameters.

Abstract: A circuit for breaking a signal path has not only a switching means but also a low-pass or bandpass filter whose frequency characteristic is switchable or bypassable. The insulation between the input and the output when the switching means is open, which decreases with frequency in the case of ordinary switching means, is compensated for by the filter which is then connected. In one embodiment of the circuit, an out-of-band signal is applied to the circuit in addition to the useful signal. The out-of-band signal is intended to be supplied permanently to an evaluation circuit, regardless of the switching position of the switching means. To this end, the out-of-band signal is tapped off downstream of the filter, and the filter is designed such that the out-of-band signal can pass through the filter. In the case of a circuit for selecting one of two inputs, at least one of the inputs is provided with a switchable or bypassable filter, and the switching means is a selection means.

Abstract: A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode.

Abstract: A voltage generator includes a detector for outputting a driving signal according to comparison results of a reference voltage and a pumping voltage, an oscillator for generating an oscillation signal in response to the driving signal and varying a period of the oscillation signal according to a level of the pumping voltage, and a pump for pumping an external voltage in response to the oscillation signal to generate the pumping voltage. The voltage generator can quickly increase a pumping voltage up to the target level and improve the efficiency of the pumping voltage by minimizing the ripple components of the pumping voltage.

Abstract: In related arts, a body voltage needs to be controlled by separately detecting external environment such as temperature. In the related art, variation such as a process parameter for each individual product has not been considered. A semiconductor integrated circuit according to the present invention includes a comparator comparing a leak current of a first conductive type transistor with a leak current of a second conductive type transistor to output a comparing result, and a conduction control signal generator outputting a signal determining a conduction state of the first conductive type transistor and a conduction state of the second conductive type transistor in a power saving control target circuit in a power saving mode based on the comparing result.

Abstract: An optimized output voltage circuit and technique obtainable without trimming is set forth. A voltage reference circuit and method devoid of trim resistors comprising a high gain amplifier, a plurality of bandgap resistors, and at least a plurality of bipolar devices interconnected across circuitry in a predetermined configuration having emitter areas greater than traditional emitter areas of traditional bipolar devices is set forth.

Abstract: To improve a depletion transistor provided between a control terminal of an output transistor and an output terminal coupled to a load not to enter a conductive state when the output transistor is in the conductive state. The output transistor is served as a source follower. Control voltages which controlling the conductive state/nonconductive state of the depletion transistor are supplied to both a control terminal (gate) and a substrate terminal (back gate) of the depletion transistor.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.

Abstract: A system to evaluate a voltage in a charge pump may include a transistor, and a transistor drain carried by the transistor with the transistor drain receiving a reference current. The system may also include a transistor gate carried by the transistor and connected to the transistor drain. The system may further include an additional transistor and an additional transistor gate carried by the additional transistor and connected to the transistor gate. The system may additionally include an additional transistor drain to receive the reference current mirrored from the additional transistor.

Abstract: A charge pump system for supplying an output voltage to a load is described. It includes a regulation circuit connected to receive the output voltage and derive an enable signal from it and multiple charge pump circuits connected in parallel to supply the output voltage. Each of the charge pump circuits is also connected to receive a clock signal and the enable signal. The system also includes one or more delay circuit elements, where a corresponding one or more, but less than all, of the charge pump circuits are connectable to receive the enable signal delayed by the corresponding delay circuit element.

Abstract: A circuit has an input for receiving a power mode control signal to indicate a low power mode. A plurality of non-inverting buffers forms a fanout signal distribution network and provides buffering of the power mode control signal for gated power domain functional circuitry. Each non-inverting buffer has an even number of serially-connected inverting gates, at least a portion providing respective outputs having a valid logic state in the low power mode. Two voltages are used, one of which is disconnected during the low power mode. The non-inverting buffers have a first inverting gate connected to a continuous voltage terminal and a second inverting gate, collectively sized larger than the first inverting gate and connected to a voltage terminal which is selectively disconnected during the low power mode from the continuous voltage terminal.

Abstract: A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one embodiment, the first orientation is vertical and the second orientation is horizontal.

Abstract: A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor.