Abstract: A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor.

Abstract: A semiconductor device operates in an active mode or a standby mode, and includes a substrate-potential power source line supplying a substrate potential which is higher in a standby mode than in an active mode, and a source-potential power source line supplying a source potential which is lower in a standby mode than in an active mode. During a mode shift from the standby mode to the active mode, a potential equalizing transistor is turned ON to pass a current flowing from the substrate-potential power source line to the source-potential power source line, to reduce the time length needed for shifting from the standby mode to the active mode.

Abstract: One embodiment of the invention includes a current mirror system. The system comprises a master circuit configured to conduct a first current in response to an activation state of an activation signal. The system also comprises a slave circuit configured to generate at least one second additional current in response to the activation state of the activation signal. Each of the at least one additional current can be proportional to the first current. The system further comprises a current path circuit that is configured as a substantial copy of the master circuit, the current path circuit being configured to conduct the first current in response to a deactivation state of the activation signal.

Abstract: A sawtooth voltage generator has a first capacitor that is charged with a variable feedback control current to provide a sawtooth output signal with a controlled amplitude. A feedback loop includes a comparator that compares a version of the sawtooth output signal with a fixed voltage reference to provide a comparator output signal to a phase frequency comparator, the output of which controls a source of the variable feedback control current. A method includes controlling the amplitude of a sawtooth output signal by charging a capacitor in a sawtooth voltage generator with a variable feedback control current; comparing a version of the sawtooth output signal with a fixed reference voltage to provide a comparator output signal; processing the comparator output signal in a phase frequency comparator to provide up/down control signals; and controlling the variable feedback control current with the up/down control signals from the phase frequency comparator.

Abstract: A core voltage generation circuit includes a comparator configured to perform a differential comparison of a reference voltage and a feedback core voltage. An amplifier is configured to amplify the external power supply voltage in response to an output signal of the comparator to generate the core voltage. A control switch is configured to form a current path of the comparator using different switch units according to a voltage level of an external power supply voltage input to the core voltage generation circuit.

Abstract: A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device.

Abstract: The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.

Abstract: The internal voltage generator of a semiconductor integrated circuit includes at least one variable reference voltage generating unit that generates a base reference voltage increased or decreased according to the variation in temperature, at least one level shifting unit that transforms the base reference voltage outputted by the at least one variable reference voltage generating unit into at least one prescribed reference voltage for generating internal voltage and outputs the transformed reference voltage, and at least one internal voltage generating unit that generates an internal voltage by using the at least one reference voltage for generating internal voltage outputted by the at least one level shifting unit.

Abstract: A bias control system for the radio frequency power amplifiers that includes a current source, a mirror current, and a bias voltage.

Abstract: A bipolar differential output circuit includes an input differential bipolar stage for receiving an input signal and generating a differential output current. An output differential pair of bipolar transistors without a bipolar tail current source responds to the input signal by providing a representative output signal. And a current mirror circuit passes current from the input differential pair to the output differential pair.

Abstract: A semiconductor integrated circuit device has a first MIS transistor of a first conductivity type, a second MIS transistor of a second conductivity type, a resistor connected in series between a first power-source line and a second power-source line, and a third MIS transistor of the first conductivity type. The third MIS transistor has a gate connected to a node where the first MIS transistor and the second MIS transistor are connected together, and a drain connected to a connection node where the second MIS transistor and the resistor are connected together.

Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

Abstract: An apparatus for generating an internal voltage includes an output-voltage detecting unit for detecting a voltage level of an internal voltage, an oscillating unit for generating a periodic signal in response to a detection signal from the output-voltage level detecting unit, a first driving-voltage level detecting unit for detecting an increase of a voltage level of a driving voltage, a second driving-voltage level detecting unit for detecting a decrease of a voltage level of the driving voltage, a period control unit for controlling a period of the periodic signal in response to output signals of the first and second driving-voltage level detecting units, and a charge pumping unit for generating the internal voltage by charge-pumping the driving voltage in response to an output signal from the period control unit.

Abstract: An integrated circuit includes a trimming signal creating section, disposed downstream of a trimming circuit in which a number of fuses are arranged in alignment, creating a trimming signal corresponding to the trimming value on the basis of a signal output from said trimming circuit and arranges blown object fuses such that every two of the blown object fuses are interposed at least one un-blown fuses in the trimming circuit. An efficient arrangement of blowing points in addition to the above arrangement of blown object fuses can reduce the area occupied by the trimming circuit.

Abstract: An adaptive bandwidth phase locked loop (PLL) includes a phase frequency detector configured to generate a comparison pulse having a pulse-width and sign corresponding to a difference between a reference frequency and a first frequency. A pulse-voltage converter is configured to generate a control voltage corresponding to the comparison pulse. An oscillator is configured to generate the output frequency corresponding to the control voltage.

Abstract: A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.

Abstract: An internal voltage generation circuit of a semiconductor device includes: a voltage detecting unit configured to detect a voltage level of an internal voltage output terminal to output a voltage detection signal; an oscillating unit configured to generate a first oscillation signal having a predefined frequency in response to the voltage detection signal; and a pumping unit configured to perform a charge pumping operation in response to the first oscillation signal and the voltage detection signal to output an internal voltage to the internal voltage output terminal, a period of the charge pumping operation being limited within an activation period of the voltage detection signal.

Abstract: A current consumption prevention apparatus includes a first current supply unit for transferring charges from a capacitor connected to a first inverter group to a capacitor connected to a second inverter group, and a second current supply unit for transferring charges of the capacitor connected to the second inverter group to the capacitor connected to the first inverter group. The current supply units are operated complementarily.

Abstract: A driving circuit is provided by the present invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between the level shifter and the buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter.

Abstract: An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NFET or PFET is directly connected to the source of the second NFET or PFET, and wherein the gate of the second NFET or PFET is at a voltage value which is equal to or lower than the drain voltage value of the second NFET or PFET in the case of an NFET and equal to or higher than the drain voltage value of the second NFET or PFET in the case of a PFET.