Abstract: A substrate according to an embodiment includes an insulating layer having a grain formed therein extending in a first direction; and a circuit pattern disposed on the insulating layer; wherein the insulating layer includes an upper surface and a plurality of outer side surfaces; wherein the plurality of outer side surfaces includes: a first outer side surface extending in the same first direction as the first direction having the grain formed in the insulating layer; and a second outer side surface extending in a second direction different from the first direction and excluding the first outer side surface, wherein the first outer side surface has a first surface roughness; and wherein the second outer side surface has a second surface roughness different from the first surface roughness.

Abstract: Embodiments of the present application provide a laser light source and a laser projection device. The laser light source includes a laser assembly and a light combination mirror assembly. The laser assembly includes at least a laser, a light emitting surface of the laser has a plurality of light emitting regions, and beams emitted from different ones of the plurality of light emitting regions are in different colors. The light combination mirror assembly includes a plurality of mirrors that are sequentially arranged along an optical transmission path of the laser, with each of the mirrors corresponding to one of the light emitting regions. The light combination mirror assembly is used to converge the beams in different colors emitted from the laser to form a white beam.

Abstract: A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<1/2×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.

Abstract: A pure copper sheet has a composition including 99.96 mass % or more of Cu, 9.0 mass ppm or more and less than 100.0 mass ppm of a total content of Ag, Sn, and Fe, and inevitable impurities as a balance, in which an average crystal grain size of crystal grains on a rolled surface is 10 ?m or more, the pure copper sheet has crystals in which crystal planes parallel to the rolled surface are a {022} plane, a {002} plane, a {113} plane, a {111} plane, and a {133} plane, and diffraction peak intensities of the individual crystal planes that are obtained by X-ray diffraction measurement by a 2?/? method on the rolled surface satisfy I {022}/(I {022}+I {002}+I {113}+I {111}+I {133})?0.15, I {002}/I {111}?10.0, and I {002}/I {113}?15.0.

Abstract: A stretchable mounting board that includes: a stretchable substrate; a mounting electrode portion on a main surface side of the stretchable substrate and containing a conductive filler and a resin; a solder portion connected to the mounting electrode portion; and an electronic component electrically connected to the mounting electrode portion with the solder portion interposed therebetween. The mounting electrode portion has a first main surface on a stretchable substrate side thereof, a second main surface on a solder portion side thereof, a first region including the first main surface, and a second region including the second main surface, and wherein, in a cross-section along a thickness direction of the mounting electrode portion passing through the first region and the second region, a sectional area of the conductive filler in the second region is larger than a sectional area of the conductive filler in the first region.

Abstract: A low dielectric substrate for high-speed millimeter-wave communication includes a quartz glass cloth with a dielectric loss tangent of 0.0001 to 0.0015 and a dielectric constant of 3.0 to 3.8 at 10 GHz, and an organic resin with a dielectric loss tangent within 80% to 150% of the dielectric loss tangent of the quartz glass cloth at 10 GHz and a dielectric constant within 50% to 110% of the dielectric constant of the quartz glass cloth at 10 GHz. This provides a low dielectric substrate for high-speed millimeter-wave communication where the low dielectric substrate makes it possible to send signals that are stable and have excellent quality with no difference in propagation time between wirings even if the substrate has an uneven resin distribution and the quartz glass cloth above and below the wirings, and the difference in dielectric loss tangent between members has been reduced to lower transmission loss.

Abstract: A mounting structure for mounting inductors to suppress cross talk and a stub effect due to a mounting land, and reduce deterioration of signal transmission characteristics. A first Bias-T inductor is mounted on a circuit board with one electrode terminal connected to a first mounting land with an axial direction of the first Bias-T inductor oriented perpendicular to the first mounting land and the one electrode terminal extends along the first mounting land. A second Bias-T inductor is mounted on the circuit board in the vicinity of the first Bias-T inductor with one electrode terminal connected to a second mounting land with an axial direction of the second Bias-T inductor inclined by 90° with respect to the axial direction of the first Bias-T inductor and the second Bias-T inductor is oriented perpendicular to the second mounting land and the one electrode terminal extends along the second mounting land.

Abstract: An electroconductive substrate including a base material and a metal wiring made of at least either of silver and copper, and the electroconductive substrate has an antireflection region formed on part or all of the metal wiring surface. This antireflection region is composed of roughened particles made of at least either of silver and copper and blackened particles finer than the roughened particles and embedded between the roughened particles. The blackened particles are made of silver or a silver compound, copper or a copper compound, or carbon or an organic substance having a carbon content of 25 wt % or more. The antireflection region has a surface with a center line average roughness of 15 nm or more and 70 nm or less. The electroconductive substrate is formed from metal wiring from a metal ink that forms roughened particles, followed by application of a blackening ink containing blackened particles.

Abstract: A ceramic carrier substrate for an electrical/electronic circuit. The substrate includes ceramic layers arranged one above the other in an interconnected structure and conductor tracks arranged on and/or in individual ceramic layers and connected to one another as the conductor structure for the electrical/electronic circuit. The interconnected structure is formed by a firing operation. A first conductor substructure is formed in a first interconnected structure subassembly which comprises at least one of the ceramic layers, and a second conductor substructure is formed in a second interconnected structure subassembly which is directly adjacent to the first interconnected structure subassembly and comprises at least one of the ceramic layers. The second conductor substructure substantially consists of high-current conductor tracks and is configured to contact a power circuit.

Abstract: A microelectronics H-frame device comprising an RF crossover includes: a stack of two or more substrates, wherein a bottom surface of a top substrate comprises top substrate bottom metallization, and wherein a top surface of a bottom substrate comprises bottom substrate top metallization, wherein the top substrate bottom metallization and the bottom substrate top metallization form a ground plane that provides isolation to allow a first signal line to traverse one or more of the top substrate and the bottom substrate without being disturbed by a second signal line traversing one or more of the top substrate and the bottom substrate at a non-zero angle relative to the first signal line, at least one of the first signal line and the second signal line passing to a second level with the protection of the ground plane, thereby providing isolation from the other signal line.

Abstract: Disclosed are an embedded circuit board and a fabrication method therefor. The embedded circuit board comprises: a circuit board body; signal transmission layers (1200), wherein the signal transmission layers are arranged on two opposite sides of the circuit board body; bonding layers, wherein the bonding layers are arranged between at least one signal transmission layer and the circuit board body and used for bonding the signal transmission layer to the circuit board body; metal bases which are embedded in the circuit board body and are electrically connected to the signal transmission layers on two opposite sides of the circuit board body; conductive parts which are arranged at the positions in the bonding layers corresponding to the metal bases, and are electrically connected to the signal transmission layer and the metal bases; and magnetic cores embedded in the circuit board body.

Abstract: Proposed is a high temperature superconducting wire manufacturing method and a high temperature superconducting wire having multiple superconducting layers formed by applying the method. The method includes a stacking process in which a pair of protective layers of superconducting wires including a substrate, a superconducting layer, and the protective layer are stacked such that the protective layers face each other, a joining process in which the protective layers facing each other are diffusion joining together by thermal treatment and become a joining protective layer, an exfoliating process in which a layered structure of an upper portion of the corresponding superconducting layer is removed such that one side of the superconducting layer is exposed to the outside, and an outermost protective layer forming process in which an outer protective layer formed of the same material as the joining protective layer is formed on the upper portion of the exposed superconducting layer.

Abstract: The conductive device includes a substrate and an electrically conductive portion. The electrically conductive portion is provided on the substrate. The electrically conductive portion includes an electrically conductive part and a low resistance conductive layer. The electrically conductive part is provided on the substrate and includes an electrically conductive particle and an organic binder. The low resistance conductive layer covers at least part of a surface of the electrically conductive part and has lower resistivity than the electrically conductive part.

Abstract: The present disclosure provides a printed circuit board with a plated through hole. The through hole covered by a solder pad at both ends of the through hole. At least two pins are plugged into the through hole, one of which with its head end being thermal contacted with one of the solder pads. Another pin's head end being thermal contacted with the other solder pad. The at least two pins are thermal contacted with one another. Thermal dissipation rate is increased with the structure of the through hole.

Abstract: In a wire drawing method, processing stability is ensured by preventing a shape from deforming non-uniformly. The wire drawing method includes: using a first wire that includes a center member, a plurality of first peripheral wires surrounding the center member, and an outer shell disposed outside the first peripheral wires; and reducing a cross-sectional diameter of the first wire by wire drawing. A shape of a cross section perpendicular to a longitudinal direction of the first peripheral wire is a substantially isosceles trapezoidal shape including a long side in contact with the outer shell, a short side in contact with the center member, and a first oblique side and a second oblique side that are in contact with the adjacent peripheral wires.

Abstract: A single-layer redistribution plate functioning as a space translator between a device under testing (“DUT”) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.

Abstract: Embodiments described herein can include multi-layer circuits within a liquid crystal polymer (LCP) material to define a 3-D interconnect structure that connects the microelectronics features, devices, components and electrical interfaces. In addition, mechanical functions can be embedded in a fashion and proximity such that the embedded electronics can interface and interact with each other as well as introduced conditions relevant to the function of the device and the outside world or environment it is exposed to.

Abstract: A printed wiring board includes an electrically insulating base film, and an electrically conductive pattern stacked on at least one surface side of the base film. An average width of multiple wiring portions included in the electrically conductive pattern is 5 ?m or greater and 20 ?m or less. Each of the wiring portions includes a seed layer and a plating layer. The plating layer includes copper crystal planes of a (111) plane, a (200) plane, a (220) plane, and a (311) plane. An intensity ratio IR220 of an X-ray diffraction intensity of the copper crystal plane (220) obtained by Equation (1) below is 0.05 or greater and 0.14 or less, IR220=I220/(I111+I220+I311)??(1) (where I111, I200, I220, I311 are respectively X-ray diffraction intensity of the (111) plane (200) plane, the (220) plane, and the (311) plane).

Abstract: The wiring board according to the present disclosure includes: a first insulating layer including insulating particles; a plurality of first conductors located on the first insulating layer at an interval of a first distance from each other; a second conductor located on the first insulating layer at an interval of a second distance from the first conductor; and a second insulating layer located on the first insulating layer to cover the first conductor and the second conductors and including the insulating particles. When a boundary portion between the first insulating layer and the second insulating layer is viewed in cross-section in the thickness direction, the ratio of a first area occupied by the insulating particles in a first boundary portion including the first distance is higher than the ratio of a second area occupied by the insulating particles in a second boundary portion including the second distance.

Abstract: A low dielectric substrate for high-speed millimeter-wave communication includes a quartz glass cloth with a dielectric loss tangent of 0.0001 to 0.0015 and a dielectric constant of 3.0 to 3.8 at 10 GHz, and an organic resin with a dielectric loss tangent within 80% to 150% of the dielectric loss tangent of the quartz glass cloth at 10 GHz and a dielectric constant within 50% to 110% of the dielectric constant of the quartz glass cloth at 10 GHz. This provides a low dielectric substrate for high-speed millimeter-wave communication where the low dielectric substrate makes it possible to send signals that are stable and have excellent quality with no difference in propagation time between wirings even if the substrate has an uneven resin distribution and the quartz glass cloth above and below the wirings, and the difference in dielectric loss tangent between members has been reduced to lower transmission loss.