Abstract: An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.

Abstract: In one aspect, a PCB is provided. The PCB includes at least one insulating layer, a blind slot, and at least one via. The at least on insulating layer includes a first surface and a second surface opposite the first surface. The blind slot is plated and formed in the at least one insulating layer, where the blind slot partially extends from the first surface to the second surface, and where the blind slot includes a conductive plating bonded along a major surface of the blind slot. The at least one via is electrically conductive and filled, where the at least one via is coupled with and extends between the conductive plating of the blind slot and the second surface of the at least one insulating layer.

Abstract: A module substrate for a semiconductor module including a wiring substrate having an upper surface and a lower surface opposite to each other and including a wiring formed therein, the wiring substrate having at least one through groove in at least one sidewall and extending in a thickness direction, and a through-groove test terminal including at least one contact pad, a surface of the contact pad being exposed from an inner wall of the through-groove, the contact pad being spaced apart from a vertical plane extending from the sidewall of the wiring substrate may be provided.

Abstract: A semiconductor package assembly includes a circuit board, a heat dissipating element and a semiconductor device. The circuit board includes a conductive pattern. The heat dissipating element is located on the circuit board, where the heat dissipating element is connected to the conductive pattern. The semiconductor device is located on the circuit board and next to the heat dissipating element, where the semiconductor device is thermally connected to the heat dissipating element through the conductive pattern.

Abstract: A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on an upper surface of the insulating layer; a first solder resist disposed on an upper surface of the insulating layer and having a height smaller than a height of the circuit pattern; and a second solder resist disposed on an upper surface of the first solder resist and including a first portion having an upper surface lower than an upper surface of the circuit pattern and a second portion having an upper surface higher than the upper surface of the circuit pattern, wherein the circuit pattern includes: a plurality of first circuit patterns disposed on an upper surface of a first region of the insulating layer, and a plurality of second circuit patterns disposed on an upper surface of a second region of the insulating layer; wherein the first portion of the second solder resist is disposed between the plurality of first circuit patterns to have an upper surface lower than an upper surface of the first circuit

Abstract: Disclosed are special component carriers made of MID-capable plastic in order to make the geometric arrangement of electrical components, such as microprocessors, LEDs, sensors, antennas and the like, on a circuit board more flexible. Said component carriers can have a standardized footprint for connecting to the circuit board and can be adapted to the terminals and the geometric arrangement of the components using individually applied conducting tracks, in particular in an LDS process. Furthermore, the specially shaped component carriers allow the electrical components to be geometrically oriented, in particular at a right angle to the circuit board and parallel to the circuit board, which is especially highly advantageous for antennas and acceleration sensors. Furthermore, SMT soldering is made possible in the pre-mounted state even for temperature-sensitive components.

Abstract: A circuit board, a preparation method thereof, and an electronic device are provided. The circuit board includes: a substrate, defining a first through-hole; a metal block, embedded in the first through-hole and fixedly connected to the substrate; a conductive line layer, arranged on at least one side surface of the substrate; wherein the conductive line layer partially covers an opening of the first through-hole on a corresponding side surface of the substrate; and a conductive channel, penetrating the conductive line layer and the metal block in turn. The conductive channel comprises a second through-hole and a conductive medium plated on a wall of the second through-hole; an end of the conductive medium is connected to the conductive line layer, and another end of the conductive medium is connected to the metal block.

Abstract: A printed circuit board (PCB) assembly is provided. The PCB assembly comprises a printed wiring board (PWB) and one or more electrical components mounted thereon. The PWB comprises a plurality of layers including conductive layers and insulative layers, where one or more of the insulative layers is a prepreg layer that is halogen-free; one or more slotted portions on a surface of the PWB, which are indented into the PWB; and one or more pads disposed on the surface of the PWB, which are paired with the one or more slotted portions. Each of the one or more electrical components is mounted on the surface of the PWB through a pair of a slotted portion and a pad.

Abstract: The disclosure provides for methods of making electrically conductive apparatus, such as circuit boards. The methods include 3D-printing a ceramic material into a ceramic substrate that includes a void. A conductive material is infused into the void. The conductive materiel forms electrically conductive connections within the apparatus. Also disclosed are apparatus formed by the methods.

Abstract: A paddle card includes a printed circuit board and a twin-axial cable. The PCB includes a first signal pad on a top surface of the PCB and a second signal pad on a bottom surface of the PCB. The second signal pad is directly below the first signal pad. The twin-axial cable includes a first signal conductor coupled to the first signal pad and a second signal conductor coupled to the second signal pad.

Abstract: In one embodiment, a grounding structure for a printed circuit board (PCB) of an information handling system includes: a first ground via electrically coupled to a ground layer of the PCB; a second ground via electrically coupled to the ground layer of the PCB; and a conductive strip electrically coupling the first ground via to the second ground via, the conductive strip providing a vertical ground reference for a signal transferred from a first surface of the PCB to a second surface of the PCB through a signal via disposed on the PCB.

Abstract: A resin multilayer substrate includes a multilayer body including resin base-material layers in a thickness direction, a side-surface conductor on at least a side surface of the multilayer body and made of a metallic material with a coefficient of thermal expansion whose difference from a coefficient of thermal expansion of the resin base-material layers in a plane direction is smaller than a difference from a coefficient of thermal expansion of the resin base-material layers in the thickness direction, a circuit component in the multilayer body and defining a circuit, and inner conductors in the multilayer body, located between the side-surface conductor and the circuit component along the side-surface conductor, and at least partially overlapping each other when viewed in the thickness direction, each of the inner conductors being one of a dummy conductor and a ground conductor.

Abstract: Described herein are systems and methods for a design method and new interconnect structures with incorporated interdigital trapezoidal tabs structures enabled with materials with either larger permittivity or permeability for improved signal integrity.

Abstract: A circuit board structure includes a first dielectric layer, first and second inner circuit layers, a conductive connection layer, a second dielectric layer, two third dielectric layers, third and fourth inner circuit layers, two conductive through vias, first and second annular retaining walls, two fourth dielectric layers, first and second external circuit layers, and third and fourth annular retaining walls. The conductive through vias penetrate the third and second dielectric layers and electrically connect the third and fourth inner circuit layers. The first and second annular retaining walls surround the conductive through vias and electrically connect the third and first and the fourth and second inner circuit layers. The third and fourth annular retaining walls are respectively disposed in the fourth dielectric layers and electrically connect the first external circuit layer and the third inner circuit layer and the second external circuit layer and the fourth inner circuit layer.

Abstract: A circuit board includes a first dielectric material, a second dielectric material, a third dielectric material, a first external circuit layer, a second external circuit layer, multiple conductive structures, and a conductive via structure. Dielectric constants of the first, the second and the third dielectric materials are different. The first and the second external circuit layers are respectively disposed on the first and the third dielectric materials. The conductive via structure at least penetrates the first and the second dielectric materials and is electrically connected to the first and the second external circuit layers to define a signal path. The conductive structures are electrically connected to each other and surround the first, the second and the third dielectric materials. The conductive structures are electrically connected to the first and the second external circuit layers to define a ground path surrounding the signal path.

Abstract: A multi-layer coating on an outer surface of a substrate includes a first layer applied directly to the outer surface of the substrate. The first layer includes diamond-like carbon (DLC) configured to mitigate metal whisker formation. A second layer is applied on a top surface of the first layer. The second layer is a conformal coating that includes a second material configured to bind to the top surface of the first layer and fill any microfractures that may form in the first layer. Optionally, a third layer is applied on a top surface of the second layer and includes DLC configured to protect the second layer from oxidation and degradation.

Abstract: A printed circuit board includes a layered substrate having a plurality of layers having an electrical connector footprint configured to receive an electrical connector. The printed circuit board includes pair anti-pads passing through the layered substrate around pairs of signal vias. The printed circuit board includes ground vias passing through the layered substrate. The ground vias are configured to receive ground pins of the electrical connector. The ground vias are located outside of the pair anti-pads. The printed circuit board includes SI vias passing through the layered substrate. The SI vias form an SI fence surrounding the corresponding pair anti-pad.

Abstract: A wiring substrate includes an insulating layer including inorganic fillers and resin, and a conductor layer formed on a surface of the insulating layer and having a conductor pattern. The surface of the insulating layer has an arithmetic average roughness Ra in the range of 0.05 ?m to 0.5 ?m, the conductor layer includes a metal film formed on the surface of the insulating layer, and the inorganic fillers include a first inorganic filler including particles such that each of the particles has a portion of a surface separated from the resin and forming a gap with respect to the resin of the insulating layer and that the metal film of the conductor layer includes part formed in the gap between the first inorganic filler and the resin.

Abstract: A coupling device for coupling a plurality of cable units to a component carrier includes a base plate that is flat in at least one plane. A connecting device is disposed on a first side of the base plate and is configured to mechanically couple the base plate to the component carrier. An opening extends through the base plate for each cable end of a plurality of cable ends of the cable units. The opening in each case is disposed on the base plate at a position corresponding to the respective cable unit.

Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.