Patents Examined by Jeremy C. Norris
  • Patent number: 11908786
    Abstract: A wiring structure includes a test pattern layer. The test pattern layer includes a test circuit pattern and a heat dissipating structure. The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ting Wei Hsu
  • Patent number: 11910521
    Abstract: Disclosed herein are apparatus and methods for a power electronics assembly that includes a printed circuit board (PCB) and an electrical insulation portion. The PCB includes a plurality of embedded power devices and a substrate layer having a plurality of metal inverse opal (MIO) portions. The electrically insulating portion is positioned between each of the MIO portions. The plurality of MIO portions is thermally coupled to the plurality of embedded power devices.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 20, 2024
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Feng Zhou, Ercan Dede, Hiroshi Ukegawa
  • Patent number: 11903128
    Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on a surface of the insulating layer such that the conductor layer includes a conductor pad, and a solder resist layer formed on the surface of the insulating layer such that the solder resist layer is covering the conductor layer and having an opening exposing the conductor pad. The conductor pad of the conductor layer has a substantially rectangular planar shape such that the conductor pads has a main surface, a pair of long sides, a pair of short sides and four corner portions, and the solder resist layer is formed such that the opening is exposing side surfaces at the long sides and 50% or more of the main surface and that the solder resist layer is covering side surfaces at the short sides.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: February 13, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Shigeto Iyoda
  • Patent number: 11903133
    Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: February 13, 2024
    Assignee: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD
    Inventors: Xianming Chen, Lei Feng, Gao Huang, Benxia Huang, Yejie Hong
  • Patent number: 11895778
    Abstract: An etching method for manufacturing a substrate structure having a thick electrically conductive layer, and a substrate structure having a thick electrically conductive layer are provided.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: February 6, 2024
    Assignee: AMULAIRE THERMAL TECHNOLOGY, INC.
    Inventors: Shih-Hsi Tai, Tung-Ho Tao, Tze-Yang Yeh
  • Patent number: 11894164
    Abstract: A stretchable conductor includes a substrate with a first major surface, wherein the substrate is an elastomeric material. An elongate wire is on the first major surface of the substrate; the wire includes a first end and a second end, and further includes at least one arcuate region between the first end and the second end. At least one portion of the arcuate region of the wire in the region has a first surface area portion embedded in the surface of the substrate and a second surface area portion unembedded on the substrate and exposed in an amount sufficient to render at least an area of the substrate in the region electrically conductive. The unembedded second surface portion of the arcuate region may lie above or below a plane of the substrate. Composite articles including a stretchable conductor in durable electrical contact with a conductive fabric are also disclosed.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 6, 2024
    Assignee: 3M INNOVATIVE PROPERTIES COMPNAY
    Inventors: Ankit Mahajan, James Zhu, Saagar A. Shah, Mikhail L. Pekurovsky, Vivek Krishnan, Kevin T. Reddy, Christopher B. Walker, Jr., Michael A. Kropp, Kara A. Meyers, Teresa M. Goeddel, Thomas J. Metzler, Jonathan W. Kemling, Roger W. Barton
  • Patent number: 11889617
    Abstract: A printed circuit board includes first and second surfaces, first and second layers, and first and second vias. The first via extends from a first layer to the second surface and includes a first portion that is on a conductive path between the first layer and the second layer and a second portion that is not on the conductive path. A length of the first portion of the first via is greater than that of the second portion of the first via. The second via extends from the second surface to the second layer. The second via includes a first portion that is on the conductive path between the first layer and the second layer and a second portion that is not on the conductive path. A length of the first portion of the second via is greater than that of the second portion of the second via.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: January 30, 2024
    Assignee: BAIDU USA LLC
    Inventors: Zhenwei Yu, Yun Ji
  • Patent number: 11889622
    Abstract: An electronic device includes a component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, an electronic component on and/or in the stack, and a cooling member with a fluid cooling unit at least partially therein. The component carrier and the cooling member are connected by a connection structure.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: January 30, 2024
    Assignee: AT&S Austria Technologie & Systemtechnik AG
    Inventor: Gerald Weis
  • Patent number: 11877391
    Abstract: An object of the present invention is to provide a conductive film that is excellent in flexibility while maintaining its sufficient transparency and conductivity, and a conductive film roll, an electronic paper, a touch panel, and a flat-panel display having the same. A conductive film having a transparent substrate and a conductive part having a fine metal wire pattern disposed on one side or both sides of the transparent substrate, wherein the fine metal wire pattern is constituted by a fine metal wire, and the conductive film satisfies the following condition (i) or (ii): (i) the fine metal wire has voids, and when the cross-sectional area of the fine metal wire is defined as SM and the total cross-sectional area of the voids included in the cross-section of the fine metal wire is defined as SVtotal on the cross-section of the fine metal wire perpendicular to the direction of drawing of the fine metal wire, SVtotal/SM is 0.10 or more and 0.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 16, 2024
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Takeshi Kamijo, Sora Hida, Tetsuro Sugimoto, Yu Tomono
  • Patent number: 11877389
    Abstract: An apparatus with an anti-tamper architecture includes a substrate and a layer of a pyrotechnic composite arranged on a surface of the substrate. The pyrotechnic composite includes a metal and a metal oxide, and the layer has a thickness of about 1 micrometer to about 10 millimeters. A reaction of the pyrotechnic composite is an exothermic reaction and at least partially fractures the substrate after the reaction is initiated.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 16, 2024
    Assignee: ROCKWELL COLLINS, INC.
    Inventors: Mark Andrew Schoelen, Thomas Michael Deppert, Reginald Bean
  • Patent number: 11877385
    Abstract: A circuit board comprises a substrate with opposite first and second sides. A pair of plated through holes (PTHs) extends along z-axis. A pair of signal traces are made on the first side of the substrate and electrically coupled to the pair of the PTHs respectively to form a differential pair. A ground metal is made on the second side of the substrate, the ground metal has a clearance made therein. The ground metal extends fully overlapping with the full signal traces to eliminate reflection noise caused by a boundary between the clearance and the metal ground.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: January 16, 2024
    Assignee: FIRST HI-TEC ENTERPRISE CO., LTD.
    Inventors: Ching-Shan Chang, Kun-Tao Tang, Tsung-Ting Tsai, Chien-Lin Chen
  • Patent number: 11877397
    Abstract: The printed circuit board includes, a first conductive layer including copper foil, an insulating base layer, and a second conductive layer including copper foil in this order, and includes a via-hole laminate that is stacked on an inner circumference and a bottom of a connection hole extending through the first conductive layer and the base layer in a thickness direction. The via-hole laminate has an electroless copper plating layer stacked on the connection hole and an electrolytic copper plating layer stacked on the electroless copper plating layer. The copper foil has copper crystal grains oriented in a (100) plane orientation, and an average crystal grain size of copper of 10 ?m or more. The electroless copper plating layer includes palladium and tin, and an amount of the palladium stacked per unit area of a surface of the copper foil is 0.18 ?g/cm2 or more and 0.40 ?g/cm2 or less.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 16, 2024
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Junichi Motomura, Koji Nitta, Shoichiro Sakai, Mari Sogabe, Mitsutaka Tsubokura, Akira Tsuchiko, Masashi Iwamoto
  • Patent number: 11871512
    Abstract: A circuit board includes a substrate, a driver circuit, at least one light-emitting element, a grounding circuit, and an antenna unit. The substrate includes a first circuit layer and a second circuit layer. The driver circuit is located on the first circuit layer. The light-emitting element is located on the first circuit layer and is electrically connected to the driver circuit, so that the driver circuit controls the light-emitting element to emit light. The grounding circuit is located on the second circuit layer and is electrically connected to the driver circuit. The grounding circuit includes a plurality of conductive traces, and the conductive traces are arranged toward one side to form a clearance area on the second circuit layer. The antenna unit is located on the first circuit layer and corresponds to the clearance area to receive and transmit a radio frequency signal.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 9, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Zhen-De Jiang, Pin-Tang Chiu, Chia-Ho Lin, Zhi-Hua Feng
  • Patent number: 11864321
    Abstract: An electrical element includes a pair of conducting elements spaced from one another, a recess receiving an electrical component, and a trough extending from a first conducting element of the pair of conducting elements to a second conducting element of the pair of conducting elements. The conducting elements are at least partially exposed in the recess.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 2, 2024
    Assignee: TE Connectivity Germany GmbH
    Inventors: Rudi Blumenschein, Andre Martin Dressel, Florian Brabetz, David Greth
  • Patent number: 11864311
    Abstract: Systems and methods for educational electronics devices such as may be assembled by non-manufacturer builders, including by personal or hobbyist individuals and by groups such as clubs or classes. Methods and systems relate to Surface Mount Device (SMD) use, measurement systems, communications skill acquisition, physical construction of educational electronics, builder construction/configuration and maintenance of devices, subsystem componentry designed for effective use in educational electronics, circuit designs that permit individual builders to construct professional quality devices, and cognitively adapted methods and systems to optimize learning and performance during and after builder assembly.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: January 2, 2024
    Assignee: HEATHKIT COMPANY, INC.
    Inventors: Andrew S. Cromarty, Donald J. Peterson, Jasen Levoy, William Charles Calhoun, David Brainerd, Ann E. Cromarty, Simon A. Cromarty
  • Patent number: 11856688
    Abstract: An adhesive film for a printed wiring board includes an adhesive layer 111 and an insulating protective layer 112. The insulating protective layer has an areal material ratio (Smr2) of 91% or less, the areal material ratio (Smr2) dividing reduced valleys from a core.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: December 26, 2023
    Assignee: Tatsuta Electric Wire & Cable Co., Ltd.
    Inventor: Masahiro Watanabe
  • Patent number: 11856694
    Abstract: The disclosure provides a circuit substrate and a method for manufacturing the same. The circuit substrate includes a wiring and a substrate having a base region and a circuit region. The base region having a first pattern is constituted by a first thermoplastic material. The circuit region having a second pattern is constituted by a second thermoplastic material. The first pattern has a portion opposite to the second pattern. The wiring is formed on the circuit region along the second pattern. The first thermoplastic material is different from the second thermoplastic material, and the second thermoplastic material includes a catalyst particle.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: December 26, 2023
    Assignee: National Taiwan University of Science and Technology
    Inventors: Chen-Hao Wang, Hsueh-Yu Chen, Guan-Cheng Tong
  • Patent number: 11849540
    Abstract: The development of stretchable, mechanically and electrically robust interconnects by printing an elastic, silver-based composite ink onto stretchable fabric. Such interconnects can have conductivity of 3000-4000 S/cm and are durable under cyclic stretching. In serpentine shape, the fabric-based conductor is enhanced in electrical durability. Resistance increases only ˜5 times when cyclically stretched over a thousand times from zero to 30% strain at a rate of 4% strain per second due to the ink permeating the textile structure. The textile fibers are ‘wetted’ with composite ink to form a conductive, stretchable cladding of the silver particles. The e-textile can realize a fully printed, double-sided electronic system of sensor-textile-interconnect integration. The double-sided e-textile can be used for a surface electromyography (sEMG) system to monitor muscles activities, an electroencephalography (EEG) system to record brain waves, and the like.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: December 19, 2023
    Assignee: THE GOVERNORS OF THE UNIVERSITY OF ALBERTA
    Inventors: Hyun-Joong Chung, Jana Rieger, Thanh-Giang La, Shide Qiu, Dylan Scott
  • Patent number: 11832387
    Abstract: A printed circuit board, on which at least one light emitting diode including at least two electrodes is mounted, includes a base member, an insulating layer disposed on the base member, a plurality of conductive pads disposed on the insulating layer and electrically connected to the light emitting diode, a plurality of via holes formed through at least one conductive pad of the plurality of conductive pads and at least a portion of each insulating layer, and filling members disposed in the plurality of via holes to electrically connect the base member to the at least one conductive pad, A distance between the plurality of via holes is ‘n’ times greater than a depth of at least one via hole of the plurality of via holes, in which ‘n’ is a positive integer greater than ‘1’ and less than ‘10’.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 28, 2023
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventor: Myeong Je Kim
  • Patent number: 11832383
    Abstract: Multi-signal vias for use with differential pair signals in electronic devices. The electronic devices include a printed circuit board having a first side and a second side opposite the first side, a first conductive trace on the first side of the substrate and a second conductive trace on the first side of the substrate. The printed circuit board also includes a shared via, which includes a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are separated by a non-conductive portion. The first conducive trace is coupled to the first conductive portion of the shared via and the second conductive trace is coupled to the second conductive portion of the shared via.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: November 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Uthayarajan A/L Rasalingam, Hock Boon Khaw