Abstract: An article of manufacture may include a dielectric having a top surface and a bottom surface. The top surface provides a planar surface corresponding to a mating surface of test equipment. The bottom surface has a relief pattern that is formed to straddle components extending above a surface of a load board for a circuit tester. Also disclosed are methods and apparatus that use this and other dielectric plates to mate test equipment to a load board of a circuit tester.

Abstract: Resistances of signal paths within a interconnect structure for linking input/output (I/O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I/O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I/O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I/O ports or link the I/O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I/O ports.

Abstract: A long-range wireless phasing voltmeter having a high impedance AC voltmeter in series between two high impedance probes. Shielding surrounds and electrically isolates the voltmeter and probes that communicate wirelessly via a pair of frequency translators, thus eliminating the cable customarily used to connect the probes and enabling measurements of the voltages, voltage differences, phases and phase difference between two conductor that may be miles apart. The signal transmitted from the first probe to the second may be analog or digital and is automatically compensated to correct the synchronization of the transmitted signal for the delay required to send it via the two translators.

Abstract: The invention relates to an information carrier (101) intended to be put into a rotary motion, said information carrier (101) comprising: display means (102) designed to display image data, said display means (102) being spatially located by a spatial position, processing means (103) for periodically sending to said display means (102) image data having the same spatial position as said display means (102). Use: Optical disc/Optical disc player.

Abstract: A non-contact tester for electronic circuits consists of an electronic circuit and independent scanning head, in combination. The electronic circuit includes a micro-fabricated wireless i/o cell and means for sending and receiving signals via the wireless i/o cell. The independent scanning head has a wireless i/o cell that is compatible with the wireless i/o cell on the electronic circuit. This enables data to be exchanged with the electronic circuit to confirm proper functioning of the electronic circuit.

Abstract: An electronic circuit unit includes a circuit board mounted within a frame member, an electronic component with a cover mounted on the circuit board, and linear terminals passing through and being mounted in the circuit board. The terminals include first and second terminal groups arranged at an interval between the respective terminals in a line. The terminal groups are arranged in a line in the vicinity of one side of the circuit board. An opening portion is provided between the first and second terminal groups, and the electronic component with the cover is mounted on the circuit board while being disposed in the opening portion. As a result, a space factor for the arrangement of the electronic component with the cover is very good, and thus it is possible to reduce a widthwise dimension of the circuit board.

Abstract: An optical semiconductor device with a multiple quantum well structure, in which well layers and barrier layers comprising various types of semiconductor layers are alternately layered, in which device well layers (6a) of a first composition based on a nitride semiconductor material with a first electron energy and barrier layers (6b) of a second composition of a nitride semiconductor material with electron energy which is higher in comparison with the first electron energy are provided, followed, seen in the direction of growth, by a radiation-active quantum well layer (6c), for which the essentially non-radiating well layers (6a) and the barrier layers (6b) arranged in front form a superlattice.

Abstract: A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.

Abstract: A conductive member has a first face adapted to be mounted on a board on which an inspection circuit is arranged and a second face adapted to be opposed to a device to be inspected. The conductive member is formed with a plurality of first through holes having a first common diameter and communicating the first face with the second face. A first contact probe is provided with a first tubular body having a second diameter which is smaller than the first diameter, and a first plunger retractably projected from one end of the first tubular body. A second contact probe is provided with a second tubular body having a third diameter which is smaller than the second diameter, and a second plunger retractably projected from one end of the second tubular body.

Abstract: A contact pin a connection device, and a method of testing. The contact pin may include a barrel (for example, a cylindrical barrel) having a screw thread on an inside wall, a contact tip formed at an end of the barrel, a spring located inside the barrel and having an end connected to the contact tip, a plunger formed at the other end of the barrel and connected to the other end of the spring, and at least one screw moving together with the screw thread. The plunger and/or the contact tip may have at least one screw, moving together with the screw thread.

Abstract: A probe card includes probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.

Abstract: A printed circuit board comprises a plurality of inner and outer holes. An electrically conductive barrel may be disposed in each outer hole, and an electrically conductive barrel and a probe may be disposed in each inner hole. The electrically conductive barrels may protrude from the bottom of the interface board at substantially similar fixed heights. Transfer paths may couple at least some of the barrels in the outer holes to selected barrels in the inner holes.

Abstract: An apparatus for use with a wafer prober and a probe card comprising a stiffening member having a feature defining a first plane. The stiffening member is mountable atop the central portion of the probe card. A reference member is provided to mount to the wafer prober and has an underside with a feature defining a second plane. When the feature of the stiffening member defining the first plane is urged against the feature of the reference member defining a second plane the probe tips of the probe card are substantially planarized relative to the wafer prober.

Abstract: Disclosed herein are an anisotropically conductive connector, by which good conductivity is retained over a long period of time even when it is used repeatedly over many times or repeatedly used under a high-temperature environment, and applications thereof. The anisotropically conductive connector is an anisotropically conductive connector having an elastic anisotropically conductive film, in which a plurality of conductive parts for connection extending in a thickness-wise direction of the film have been formed.

Abstract: An inspection system for inspecting characteristics of an active matrix panel before formation of OLEDs includes: a roller contact probe having a conductive material on at least a surface thereof and sequentially contacting pixel electrodes formed on the active matrix panel while rotating; probe control circuits having capability to apply a voltage necessary for measurement to TFT arrays including pixel electrodes with which the roller contact probe is in contact; and a computer measuring currents flowing through the TFT arrays to which a voltage is applied and statistically processing the measurement results.

Abstract: Signal probing systems are provided. One such signal probing system includes: a socket configured to be electrically coupled to a processor, a printed circuit board (PCB), a separation layer that is located between the socket and the PCB, compensation circuits that each include a resistor and a capacitor coupled in parallel, and an adapter that is attached to the PCB and that is configured to be electrically coupled to a motherboard, wherein the PCB is configured to route respective probed signals through the compensation circuits, the respective probed signals being responsive to respective signals traveling between the processor and the motherboard. Methods and other systems are disclosed.

Abstract: A built-in component type multilayer wiring board includes at least one resin layer and at least one frame resin layer. The resin layer includes electronic components buried therein. The frame resin layer includes at least one of glass cloth, filler and nonwoven fabric. The frame resin layer includes no electronic component.

Abstract: A gain-phase detector differentially processes the outputs from two logarithmic amplifiers to provide ratiometric gain measurement, thereby eliminating intercept as a parameter. Hard-limited outputs from the dual amplifiers are multiplied in a logarithmic scalable phase detector core to provide a calibrated phase measurement output. In the preferred embodiment, two logarithmic amplifiers and other circuitry are co-integrated on a single substrate to provide a high degree of matching between the amplifiers, thereby canceling errors in the individual frequency responses of the individual amplifiers, extending the usable frequency response, and improving effective noise figure. Other numbers of logarithmic amplifiers can be used, and their various outputs can be added, subtracted, multiplied and combined in other manners to produce continuous products, continuous quotients, mixtures of products and quotients, etc., all of RF demodulated signals.

Abstract: A cantilever probe has an elbow for bonding to a dual plane fixture plate for a highly stiff and precise angled fixture of the bonded cantilever probe with minimal real estate consumption. The cantilever probe may feature a tip positioning pin and an elbow positioning pin fitting into corresponding holes of the fixture plate and a sacrificial assembly plate. Separate fan-out beams may be attached to the fixture plate and conductively connected to respective elbows once the cantilever probes are fixed. The fan-out beams in turn may be conductively connected with their respective peripheral ends to large pitch apparatus terminals of a circuit board. A probe apparatus may be easily customized by providing varying drill patterns of the positioning holes for fan-out beams and cantilever probes to match pitch requirements of the tested circuit chips.

Abstract: In one embodiment, a method for extracting C-V characteristics of ultra-thin oxides includes coupling a device under test to a testing structure, in which the device under test includes a plurality of transistors. Alternatively, the device under test includes a plurality of varactors. The method further includes inputting a radio frequency signal of at least one GHz into the testing structure, de-embedding the parasitics of the testing structure, inputting a bias into the device under test, determining the capacitance density per gate width of the device under test, plotting capacitance density per gate width versus gate length to obtain a first curve, and determining a slope of the first curve. These steps are repeated for one or more additional biasing conditions, and the determined slopes are plotted on a capacitance density per voltage graph to obtain a C-V curve for the device under test.