Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.

Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an inter-layer insulation film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Abstract: An assembly of a semiconductor die attached to a substrate is made with a composition comprising compounds that contain an oxazoline functionality and an electron acceptor or an electron donor functionality. Electron donor functionalities include styrenic, cinnamyl, and vinyl ether groups. Electron acceptor functionalities include maleimide, acrylate, fumarate, and maleate groups. An exemplary compound has the structure: formula (I).

Abstract: A display substrate includes an insulating substrate, a thin film transistor, a contact electrode, and a pixel electrode. The thin film transistor includes a control electrode, a semiconductor pattern, a first electrode, and a second electrode. The control electrode is on the insulating substrate. The semiconductor pattern is on the control electrode. The first electrode is on the semiconductor pattern. The second electrode is spaced apart from the first electrode on the semiconductor pattern. The contact electrode includes a contact portion and an undercut portion. The contact portion is electrically connected to the second electrode to partially expose the semiconductor pattern. The undercut portion is electrically connected to the contact portion to cover the semiconductor pattern. The pixel electrode is electrically connected to the second electrode through the contact portion of the contact electrode.

Abstract: Methods and apparatus are provided for reducing substrate leakage current of lateral RESURF diode devices. The diode device (60, 60?, 100) comprises first (39) and second (63) surface terminals overlying a semiconductor substrate (22) coupled to P (38, 32, 26) and N (24, 30, 46) type regions providing the diode action. An unavoidable parasitic vertical device (54, 92) permits leakage current to flow from the first terminal (39) to the substrate (22). This leakage current is reduced by having the diode device second terminal (63) comprise both N (46) and P (62) type regions coupled together by the second terminal (63). This forms a shorted base-collector lateral transistor (72) between the first (39) and second (63) terminals to provide the diode function. The gain of this lateral transistor (72) increases the proportion of first terminal (39) current that flows to the second terminal (63) rather than the substrate (22).

Abstract: A semiconductor device provided with a temperature detection function having a high temperature detection accuracy for improving the ESD resistance of a temperature detection diode. The semiconductor device has a semiconductor element. A temperature detection diode is used to detect the temperature of the semiconductor element and an ambient temperature of the semiconductor element. A protection diode is connected between a cathode of the temperature detection diode and a ground side of the semiconductor element when the semiconductor element is activated.

Abstract: A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor dielectric. In addition, the control region may comprise a monocrystalline material.

Abstract: An electron source include a first cathode electrode disposed over a substrate and terminated to provide electrons; an emitter layer disposed over the cathode electrode and formed from one or plurality vertically aligned and mono-dispersed nano-structures that are truncated to the same length, embedded in a solid matrix and protruding above the surface for emitting electrons; an insulator disposed over the emitter layer and having one or plurality of apertures, each is self-aligned with and exposes one nano-structure in the emitter layer; and a second gate electrode disposed over the insulator, having one or plurality of apertures self-aligned with the apertures in the insulator and terminated to extract electrons from the exposed nano-structures through the apertures. The gate aperture is substantially less than one micrometer and the gated nano-structures can have a density on the order of 108/cm2.

Abstract: A magnetic random access memory described in embodiments of the present invention comprises a conductive line, a soft magnetic material which surrounds the conductive line, a gap disposed in a part of the soft magnetic material, and a magneto-resistive element in which a part of a vertical magnetization film as a magnetic free layer is positioned in the gap and in which a vertical magnetization film as a magnetic pinned layer is positioned outside the gap.

Abstract: A hole transporting region made of a hole transporting material, an electron transporting region made of an electron transporting material, and a mixed region (light emitting region) in which both the hole transporting material and the electron transporting material are mixed and which is doped with a triplet light emitting material for red color are provided in an organic compound film, whereby interfaces between respective layers which exist in a conventional lamination structure are eliminated, and respective functions of hole transportation, electron transportation, and light emission are exhibited. In accordance with the above-mentioned method, the organic light emitting element for red color can be obtained in which power consumption is low and a life thereof is long. Thus, the display device and the electric device are manufactured by using the organic light emitting element.

Abstract: A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

Abstract: A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

Abstract: A thin film transistor composed of a semiconductor layer including an optionally substituted indolocarbazole.

Abstract: A method of manufacturing a semiconductor device includes forming isolation regions, a gate insulator film and gate electrodes, implanting in the silicon substrate with impurity ions, annealing to recover crystallinity of the implanted silicon substrate without diffusing the impurity ions, depositing an interlayer insulator film on the isolation regions, the silicon substrate, and the gate electrodes, and heating the silicon substrate by irradiating a light having a wavelength that the light is absorbed by the silicon substrate without being absorbed by the interlayer insulator film, activating the impurity ions so as to form source and drain regions.

Abstract: A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

Abstract: There is provided a semiconductor light emitting diode and a method of manufacturing the same that enable voltage in the forward direction to be decreased while allowing light extraction efficiency to be improved. This semiconductor light emitting diode is formed by a substrate, a light emitting portion that is disposed on one main surface of the substrate, a first electrode that is disposed on the light emitting portion, a pad electrode that is disposed on the first electrode, concave portions that are formed on at least a portion of the one main surface of the substrate, and a conductive layer that is formed from a conductive material that is disposed in the concave portions and reflects light emitted from the light emitting portion.

Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

Abstract: Provided are a vertical GaN-based LED and a method of manufacturing the same. The vertical GaN-based LED includes an n-electrode. An AlGaN layer is formed under the n-electrode. An undoped GaN layer is formed under the AlGaN layer to provide a two-dimensional electron gas layer to a junction interface of the AlGaN layer. A GaN-based LED structure includes an n-type GaN layer, an active layer, and a p-type GaN layer that are sequentially formed under the undoped GaN layer. A p-electrode is formed under the GaN-based LED structure. A conductive substrate is formed under the p-electrode.

Abstract: A semiconductor device include a plurality of active element cells including first element regions of a first conductivity type and second element regions of a second conductivity type, the second element regions disposed between the first element regions; and isolation regions disposed between the active element cells so as to isolate the active element cells from each other, the isolation regions being filled with a plurality of semi-insulating particles including granular insulators covered by semiconductor films.