Patents Examined by Jerome Jackson
  • Patent number: 9801236
    Abstract: A band heater assembly for heating an object includes a band heater that extends around at least a portion of a perimeter of the object. The band heater includes a cable and a band. The cable includes a resistive element, a first cable end and a second cable end. The resistive element generates thermal energy based on a current received from a power source. The first cable end and the second cable end are connected to respective ends of the band heater assembly. The band is connected to the cable and transfers a first portion of the thermal energy to an exterior surface of the object. At least a portion of the cable is exposed from the band heater to contact the exterior surface when the band heater assembly is connected to the object.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 24, 2017
    Assignee: BACKER EHP INC.
    Inventors: Stacy Springer, Ronald R. Barnes, Robert Cockrell, Lucas L. Fowler, Alvin L. Slayton
  • Patent number: 9786740
    Abstract: A semiconductor device of according to an embodiment of the present disclosure includes a n-type SiC layer; a SiC region provided on the n-type SiC layer and containing H (hydrogen) or D (deuterium) in an amount of 1×1018 cm?3 or more and 1×1022 cm?3 or less; and a metal layer provided on the SiC region.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: October 10, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Takashi Shinohe
  • Patent number: 9773874
    Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: September 26, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuo Fujiwara, Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui
  • Patent number: 9761775
    Abstract: A light source may comprise a thermally conductive frame comprising a base and a faceted portion extending from the base. The faceted portion may comprise a plurality of facets spaced circumferentially thereabout. Additionally, a hollow passageway may extend through the base and axially through the faceted portion. A plurality of LED chips may be arranged on the plurality of facets to provide an emission of light in an arc of 360 degrees.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: September 12, 2017
    Assignee: EPISTAR CORPORATION
    Inventor: Densen Cao
  • Patent number: 9761737
    Abstract: A highly reliable semiconductor device which uses an oxide semiconductor and in which a change in the electrical characteristics is suppressed is provided. The semiconductor device includes an island-shaped semiconductor layer over a base insulating layer, a pair of electrodes over the semiconductor layer, a barrier layer in contact with undersurfaces of the electrodes, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The semiconductor layer contains an oxide semiconductor. The base insulating layer contains silicon oxide or silicon oxynitride. The electrodes each contain Al, Cr, Cu, Ta, Ti, Mo, or W. The barrier layer contains oxide containing one or more metal elements contained in the oxide semiconductor. Furthermore, the electrodes and the barrier layer extend to the outside of the semiconductor layer when seen from above.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tetsuhiro Tanaka
  • Patent number: 9761578
    Abstract: The present invention relates to a display device including a static electricity discharge circuit. The display device according to an exemplary embodiment of the present invention includes: a thin film transistor array panel including a display area including a plurality of pixels and a peripheral area around the display area; a signal wire positioned at the peripheral area; and a static electricity discharge circuit unit positioned at the peripheral area and connected to the signal wire, wherein the static electricity discharge circuit unit includes a first portion and a second portion positioned at a same layer as a portion of the signal wire and facing each other with a separation space therebetween, and a connecting member positioned at a different layer from the first portion and the second portion and electrically connecting the first portion and the second portion.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: September 12, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeo Geon Yoon, Hyung Gi Jung
  • Patent number: 9748370
    Abstract: To prevent a malfunction of an overcurrent protection circuit without increasing an on-voltage, and to suppress a short circuit capacity, thus further reducing a switching loss, a trench gate IGBT is provided in which is incorporated a sense IGBT connected in parallel to a main IGBT, where only the sense IGBT portion includes a p-type channel region all over in a semiconductor substrate between adjacent parallel striped trenches, so that the capacitance of the MOS gate of the sense IGBT is smaller than the capacitance of the MOS gate of the main IGBT.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 29, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keishirou Kumada
  • Patent number: 9748422
    Abstract: A semiconductor nanocrystal include a first I-III-VI semiconductor material and have a luminescence quantum yield of at least 10%, at least 20%, or at least 30%. The nanocrystal can be substantially free of toxic elements. Populations of the nanocrystals can have an emission FWHM of no greater than 0.35 eV.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: August 29, 2017
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Peter Matthew Allen, Moungi G. Bawendi
  • Patent number: 9748315
    Abstract: A flexible display device including a substrate; a driving element layer including a plurality of thin film transistors on the substrate; a display element layer including organic light-emitting diodes electrically connected to the thin film transistors on the driving element layer; a light transmissive layer on the display element layer and configured to adjust a neutral plane of the flexible display device to lie at the driving element layer and the display element layer when the flexible display device is bent; and a back plate film attached to a back side of the substrate and having a cut portion formed in a center region where the flexible display device is bent.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: August 29, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventor: TaeWoo Kim
  • Patent number: 9748260
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: August 29, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 9735355
    Abstract: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: August 15, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: R. Stanley Williams
  • Patent number: 9735327
    Abstract: Disclosed are a light emitting device and a method of manufacturing the same. The light emitting device includes a support substrate, a reflective ohmic contact layer on the support substrate, a functional complex layer including a process assisting region and ohmic contact regions divided by the process assisting region on the reflective ohmic contact layer, and a light emitting semiconductor layer including a second conductive semiconductor layer, an active layer, and a first conductive semiconductor layer on each ohmic contact region.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: August 15, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventor: June O Song
  • Patent number: 9725306
    Abstract: Disclosed is a MEMS device having lower and upper chambers with a similar pressure and/or a similar gaseous chemistry. The MEMS device includes a top MEMS plate and a bottom MEMS plate. The MEMS device also includes a lower chamber between the bottom MEMS plate and the top MEMS plate, and an upper chamber between the top MEMS plate and a sealing layer. The top MEMS plate includes at least one segment that is narrower than the bottom MEMS plate, thereby causing the lower and upper chambers to have a similar pressure and/or a similar gaseous chemistry. In another implementation, the top MEMS plate has at least one through-hole, thereby causing the lower and upper chambers to have a similar pressure and/or a similar gaseous chemistry.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: August 8, 2017
    Assignee: Newport Fab, LLC
    Inventors: Michael J. DeBar, David J. Howard
  • Patent number: 9721901
    Abstract: Disclosed is a thin-film transistor substrate including: a substrate; a thin-film transistor formed on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; an identification (ID) mark formed on the substrate; and a metal layer contacting an upper surface of the ID mark.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jihyeon Ryu
  • Patent number: 9722190
    Abstract: The present invention relates to the use of a square planar transition metal complex as dopant, charge injection layer, electrode material or storage material.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: August 1, 2017
    Assignee: Novaled GmbH
    Inventors: Olaf Zeika, Rene Dathe, Steffen Willmann, Ansgar Werner
  • Patent number: 9721827
    Abstract: One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Wei-Fan Lee, Yuan-feng Chao, Yen Chuang
  • Patent number: 9711745
    Abstract: A high efficient white emission light emitting element having peak intensity in each wavelength region of red, green, and blue is provided. Specifically, a white emission light emitting element having an emission spectrum that is independent of current density is provided. A first light emitting layer 312 exhibiting blue emission and a second light emitting layer 313 containing a phosphorescent material that generates simultaneously phosphorescent emission and excimer emission are combined. In order to derive excimer emission from the phosphorescent material, it is effective to disperse a phosphorescent material 323 having a high planarity structure such as platinum complex at a high concentration of at least 10 wt % to a host material 322. Further, the first light emitting layer 312 is provided to be in contact with the second light emitting layer 313 at the side of an anode. Ionization potential of the second light emitting layer 313 is preferably larger by 0.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: July 18, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroko Yamazaki
  • Patent number: 9705071
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
  • Patent number: 9704863
    Abstract: A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer of a first material and a second nanosheet FET structure having second inner spacer of a second material. The first material is different than the second material.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 9704854
    Abstract: A DC-to-DC converter includes: a substrate having a switching element region defined by an isolation layer; a transistor formed over the switching element region; a landing plate formed over the isolation layer; a capacitor formed over the landing plate and includes a bottom plate, a dielectric layer and a top plate; multi-layer metal lines disposed in an upper portion of the transistor and coupled with the transistor; and an interconnection portion coupled with the multi-layer metal lines to electrically connect the transistor with the capacitor.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: July 11, 2017
    Assignee: SK Hynix Inc.
    Inventors: Heon-Joon Kim, Jae-Ho Hwang