Forming a hybrid channel nanosheet semiconductor structure
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer of a first material and a second nanosheet FET structure having second inner spacer of a second material. The first material is different than the second material.
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Semiconductor structures or devices may be embodied as field effect transistors (FETs), such as metal-oxide-semi conductor FETs (MOSFETs). One or more such FETs may comprise an integrated circuit (IC or chip). As ICs are being scaled to smaller dimensions, stacked nanosheet FETs, or nanosheet FETs, have been developed to increase effective conduction width in a given area. A nanosheet is a nanostructure with a thickness in a scale ranging from, e.g., about 1 to 100 nanometers (nm). A nanosheet FET is a FET that is formed by stacking multiple such nanostructures.
SUMMARYIllustrative embodiments of the invention provide techniques for fabricating nanosheet semiconductor structures.
For example, in one embodiment, a method for forming a nanosheet semiconductor structure comprises forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having a second inner spacer comprised of a second material. The first material is different than the second material. In one example, the first nanosheet FET structure is an n-type FET structure and the second nanosheet FET structure is a p-type FET structure. The first nanosheet FET structure and the second nanosheet FET structure are collectively formed to construct a hybrid channel nanosheet semiconductor structure.
For example, the forming step further comprises creating a first inner spacer formation within a first silicon germanium (SiGe) channel comprised in a first channel region of a first FET region, and a second inner spacer formation within a second SiGe channel comprised in a second channel region of a second FET region. The first SiGe channel is formed from one or more SiGe nanosheets and the second SiGe channel is formed from one or more second SiGe nanosheets. A first sacrificial liner is deposited on the first FET region and a second sacrificial liner is deposited on the second FET region. A mask is formed on the second sacrificial liner, and a source/drain region is formed on a first silicon (Si) channel of the first channel region. The first Si channel is formed from one or more first Si nanosheets. The mask and the first and second sacrificial liners are removed. A third inner spacer formation is created within a second Si channel comprised in the second channel region, and a source/drain region is formed on the second SiGe channel. The second Si channel is formed from one or more second Si nanosheets. The first source/drain region is filled with a first oxide and the second source/drain region is filled with a second oxide. A first gate of the first FET region is replaced with a first metal and the first SiGe channel is replaced with a first work function metal. A second gate of the second FET region is replaced with a second metal and the second Si channel is replaced with a second work function metal.
By way of further example, creating the first inner spacer formation comprises forming a first divot within the first SiGe channel and filling the first divot with a first ceramic material, and creating the second inner spacer formation comprises forming a second divot within the second SiGe channel and filling the second divot with a second ceramic material. For example, the first and/or ceramic material may be comprised of silicon-boron-carbide-nitride (SiBCN). In one illustrative embodiment, creating the third inner spacer region comprises forming a divot within the second Si channel and filling the divot with a silicate glass. For example, the silicate glass may be silicon oxycarbide (SiCO).
In another embodiment, a nanosheet semiconductor structure comprises a first nanosheet FET structure having a first inner spacer comprised of a first material, and a second nanosheet FET structure having a second inner spacer comprised of a second material. The first material is different than the second material.
In a further embodiment, an integrated circuit comprises a first nanosheet FET structure having a first inner spacer comprised of a first material, and a second nanosheet FET structure having a second inner spacer comprised of a second material. The first material is different than the second material.
These and other exemplary embodiments of the invention will be described in or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.
In illustrative embodiments, techniques are provided for fabricating semiconductor devices comprised of one or more FETs. More particularly, illustrative embodiments provide techniques for fabricating semiconductor devices comprised of one or more hybrid channel nanosheet FETS. As will be explained in illustrative embodiments, such fabrication techniques advantageously improve performance of semiconductor devices. While illustrative embodiments are described herein with respect to hybrid channel nanosheet FETs, alternative embodiments may be implemented with other types of semiconductor structures.
Furthermore, it is to be understood that embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to fabrication (forming or processing) steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the steps that may be used to form a functional integrated circuit device. Rather, certain steps that are commonly used in fabricating such devices are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, layers, regions, or structures, and thus, a detailed explanation of the same or similar features, elements, layers, regions, or structures will not be repeated for each of the drawings. It is to be understood that the terms “about,” “approximately” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error is present such as, by way of example only, 1% or less than the stated amount. Also, in the figures, the illustrated scale of one layer, structure, and/or region relative to another layer, structure, and/or region is not necessarily intended to represent actual scale.
Semiconductor structure 100 in
It is to be understood that the methods discussed herein for fabricating semiconductor structures can be incorporated within semiconductor processing flows for fabricating other types of semiconductor devices and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with embodiments can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein.
Furthermore, various layers, regions, and/or structures described above may be implemented in integrated circuits (chips). The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope or spirit of the invention.
Claims
1. A method for fabricating a nanosheet semiconductor structure, the method comprising:
- forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having a second inner spacer comprised of a second material;
- wherein the first material is different than the second material; and
- wherein forming the first nanosheet FET structure and the second nanosheet FET structure comprises: creating a first inner spacer formation within a first silicon germanium (SiGe) channel comprised in a first channel region of a first FET region and a second inner spacer formation within a second SiGe channel comprised in a second channel region of a second FET region, wherein the first SiGe channel is formed from one or more first SiGe nanosheets and the second SiGe channel is formed from one or more second SiGe nanosheets; depositing a first sacrificial liner on the first FET region and a second sacrificial liner on the second FET region; forming a mask on the second sacrificial liner; forming a first source/drain region along a first silicon (Si) channel of the first channel region, wherein the first Si channel is formed from one or more first Si nanosheets; removing the mask and the first and second sacrificial liners; creating a third inner spacer formation within a second Si channel comprised in the second channel region, wherein the second Si channel is formed from one or more second Si nanosheets; forming a second source/drain region along the second SiGe channel; filling the first source/drain region with a first oxide and the second source/drain region with a second oxide; replacing a first gate of the first FET region with a first metal and the first SiGe channel with a first work function metal; and replacing a second gate of the second FET region with a second metal and the second Si channel with a second work function metal.
2. The method of claim 1, where in the first nanosheet FET structure is an n-type FET structure and the second nanosheet FET structure is a p-type FET structure.
3. The method of claim 1, wherein the first channel region is formed via etching.
4. The method of claim 1, further comprising:
- forming a first stack on the first FET region and a second stack on the second FET region, wherein the first stack comprises a first substrate, the one or more first Si nanosheets, and the one or more first SiGe nanosheets, and wherein the second stack comprises the second substrate, the one or more second Si nanosheets, and the one or more second SiGe nanosheets;
- forming a first pad insulator on the first channel region and a second pad insulator on the second channel region;
- forming a first gate on the first pad insulator and a second gate on the second pad insulator;
- forming a first hard mask on the first gate and a second hard mask on the second gate;
- forming a first spacer on the first channel region, the first gate, and the first hard mask, and a second spacer on the second channel region, the second gate, and the second hard mask, wherein each spacer comprises silicon mononitride (SiN); and
- forming the first channel region from the first stack and the second channel region from the second stack.
5. The method of claim 4, wherein the first substrate is comprised of Si.
6. The method of claim 1, wherein creating the first inner spacer formation comprises forming a first divot within the first SiGe channel and filling the first divot with a first ceramic material, and wherein creating the second inner spacer formation comprises forming a second divot within the second SiGe channel and filling the second divot with a second ceramic material.
7. The method of claim 6, wherein the first ceramic material is comprised of silicon-boron-carbide-nitride (SiBCN).
8. The method of claim 6, wherein the first divot is formed via etching.
9. The method of claim 1, wherein creating the third inner spacer region comprises forming a divot within the second Si channel and filling the divot with a silicate glass.
10. The method of claim 9, wherein the silicate glass is silicon oxycarbide (SiCO).
11. The method of claim 1, wherein the first and second source/drain regions are formed via an epitaxial growth process.
12. The method of claim 1, wherein the first and second gates are comprised of polysilicon, and wherein replacing the first and second gates comprises removing the first and second gates via a polysilicon pull process.
13. The method of claim 1, wherein replacing the first Si channel comprises performing a Si channel release, and wherein replacing the second SiGe channel comprises performing a SiGe channel release.
14. The method of claim 1, wherein the first metal is comprised of tungsten (W).
15. The method of claim 1, further comprising performing a first chemical mechanical planarization (CMP) process after replacing the first gate and the first Si channel, and a second CMP process after replacing the second gate and the second SiGe channel.
16. The method of claim 1, wherein at least one of the first work function metal and the second work function metal is deposited via a conformal atomic layer deposition (ALD) process.
17. The method of claim 1, wherein at least one of the first metal and the second is deposited via a plasma-enhanced chemical vapor deposition (PECVD) process.
18. The method of claim 15, further comprising forming a first gate cap layer on the first FET region and a second gate cap layer on the second FET region.
19. The method of claim 18, wherein forming the first gate cap layer and the second gate cap layer comprises etching the first metal and the second metal to form recesses within the first metal and the second metal, depositing gate cap material within the recesses, and performing at least a third CMP process to remove excess portions of the deposited gate cap material.
20. The method of claim 19, wherein the gate cap material comprises SiN.
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Type: Grant
Filed: Sep 9, 2016
Date of Patent: Jul 11, 2017
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Kangguo Cheng (Schenectady, NY), Peng Xu (Guilderland, NY)
Primary Examiner: Jerome Jackson, Jr.
Assistant Examiner: Bo Fan
Application Number: 15/260,509
International Classification: H01L 27/092 (20060101); H01L 29/66 (20060101); H01L 21/02 (20060101); H01L 21/306 (20060101); H01L 29/10 (20060101); H01L 21/8238 (20060101); H01L 21/8258 (20060101); H01L 21/28 (20060101); H01L 21/321 (20060101); H01L 29/06 (20060101);