Patents Examined by Jerome Jackson
  • Patent number: 9634176
    Abstract: A method for manufacturing a crystalline silicon-based solar cell having a photoelectric conversion section includes a silicon-based layer of an opposite conductivity-type on a first principal surface side of a crystalline silicon substrate of a first conductivity-type, and a collecting electrode formed by an electroplating method on a first principal surface of the photoelectric conversion section. By applying laser light from a first or second principal surface side of the photoelectric conversion section, an insulation-processed region his formed where a short-circuit between the first principal surface and a second principal surface of the photoelectric conversion section is eliminated. On the collecting electrode and/or the insulation-processed region, a protecting layer s formed for preventing diffusion of a metal contained in the collecting electrode into the substrate.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: April 25, 2017
    Assignee: KANEKA CORPORATION
    Inventors: Daisuke Adachi, Masanori Kanematsu, Hisashi Uzu
  • Patent number: 9627265
    Abstract: A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Chun-Wai Ng, Ruey-Hsin Liu
  • Patent number: 9627533
    Abstract: A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 18, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ZEON CORPORATION
    Inventors: Ravi K. Dasaka, Sebastian U. Engelmann, Nicholas C. M. Fuller, Masahiro Nakamura, Richard S. Wise
  • Patent number: 9627200
    Abstract: The present disclosure provides systems, processes, articles of manufacture, and compositions that relate to core/shell semiconductor nanowires. Specifically, the disclosure provides a novel semiconductor material, CdSe/ZnS core/shell nanowires, as well as a method of preparation thereof. The disclosure also provides a new continuous flow method of preparing core/shell nanowires, including CdSe/CdS core/shell nanowire and CdSe/ZnS core/shell nanowires.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: April 18, 2017
    Assignee: US Nano LLC
    Inventors: Anthony C. Onicha, Louise E. Sinks, Stefanie L. Weber
  • Patent number: 9620714
    Abstract: Oxidation treatment is performed to the surface of a substrate provided with a photocatalytic conductive film and an insulating film; treatment with a silane coupling agent is performed, so that a silane coupling agent film is formed and the surface of the substrate is modified to be liquid-repellent; and the surface of the substrate is irradiated with light of a wavelength (less than to equal to 390 nm) which has energy of greater than or equal to a band gap of a material for forming the photocatalytic conductive film, so that only the silane coupling agent film over the surface of the photocatalytic conductive film is decomposed and the surface of the photocatalytic conductive film can be modified to be lyophilic.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: April 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Gen Fujii, Erika Takahashi
  • Patent number: 9620418
    Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Liang Li, Wei Lu, Lian Choo Goh, Yung Fu Alfred Chong, Fangyue Liu, Alex See
  • Patent number: 9614051
    Abstract: A method for fabricating a semiconductor device includes providing a substrate; and forming at least one dummy gate structure on the substrate. The method also includes forming doping regions in the substrate at both sides of the dummy gate structure; forming an interlayer dielectric layer on the d the dummy gate structure; performing a first step thermal annealing process to increase a density of the interlayer dielectric layer; and activating doping ions for a first time without an excess diffusion of the doping ions in the doping region; and removing the dummy gate structure to expose the surface of the substrate to form a trench in the annealed interlayer dielectric layer. Further, the method also includes forming a gate dielectric layer on the surface of the substrate on bottom of the trench; and performing a second step thermal annealing process to activate the doping ions for a second time.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: April 4, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jie Zhao
  • Patent number: 9613830
    Abstract: A method of making a semiconductor device can include providing a temporary carrier with a semiconductor die mounting site, and forming conductive interconnects over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted at the semiconductor die mounting site. The conductive interconnects and semiconductor die can be encapsulated with mold compound. First ends of the conductive interconnects can be exposed. The temporary carrier can be removed to expose second ends of the conductive interconnects opposite the first ends of the conductive interconnects. The conductive interconnects can be etched to recess the second ends of the conductive interconnects with respect to the mold compound. The conductive interconnects can comprise a first portion, a second portion, and an etch stop layer disposed between the first portion and the second portion.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 4, 2017
    Assignee: Deca Technologies Inc.
    Inventors: Christopher M. Scanlan, William Boyd Rogers, Craig Bishop
  • Patent number: 9607885
    Abstract: Various embodiments provide semiconductor devices and fabrication methods. In an exemplary method, a dielectric layer can be formed on a semiconductor substrate. A plurality of pillar structures having a matrix arrangement can be formed on the dielectric layer. A plurality of sidewall spacers can be formed on the dielectric layer. Each sidewall spacer can be formed on a sidewall surface of one of the plurality of pillar structures. A distance between adjacent pillar structures in a same row or in a same column can be less than or equal to a double of a thickness of the each sidewall spacer on the sidewall surface. The plurality of pillar structures can be removed. The dielectric layer can be etched using the plurality of sidewall spacers as an etch mask to form a plurality of trenches or through holes in the dielectric layer.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: March 28, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Peter Zhang, Steven Zhang
  • Patent number: 9608403
    Abstract: A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Robert K. Leidy, Jeffrey C. Maling
  • Patent number: 9607945
    Abstract: A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed to have output wires extending from the respective divisional elements connected to corresponding output pads without crossing other output wires. Arranged on the IC chip are output bumps in association with the respective output pads. A rewiring layer is provided having output coupling wires for connecting together the bumps that belong to the same power element and connecting them further to an external output electrode.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: March 28, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Kunihiro Komiya
  • Patent number: 9601580
    Abstract: A semiconductor device includes a first transistor having a first conductivity type SiC layer, a second conductivity type SiC well region, a first conductivity type SiC first source region, a first conductivity type SiC first drain region, and a first gate electrode provided on the well region sandwiched between the first source region and the first drain region. The device includes a second transistor having a second conductivity type SiC second source region, a second conductivity type SiC second drain region provided on the SiC layer, and a second gate electrode provided on the SiC layer sandwiched between the second source region and the second drain region. There is an angle between a direction of a channel forming portion of first transistor and that of the second transistor. The device includes an element isolation region having a bottom positioned in the SiC layer.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke Iijima, Kazuto Takao, Tatsuo Shimizu
  • Patent number: 9601511
    Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 21, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION, STMicroelectronics, Inc.
    Inventors: Maud Vinet, Kangguo Cheng, Bruce Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec, Qing Liu
  • Patent number: 9601494
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices include an interlayer insulating layer on a semiconductor substrate, contact pads on the semiconductor substrate and penetrating the interlayer insulating layer, a stopping insulating layer on the interlayer insulating layer, storage electrodes on the contact pads, upper supporters between upper parts of the storage electrodes, side supporters between the storage electrodes and the upper supporters, a capacitor dielectric layer on the storage electrodes, the side supporters, and the upper supporters, and a plate electrode on the capacitor dielectric layer.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Eun Kim, Dae-Ik Kim, Seung-Jun Lee, Young-Seung Cho
  • Patent number: 9601446
    Abstract: A method of forming a bond pad structure is provided. The method includes forming a first conductive layer over a substrate and depositing a first dielectric layer over the first conductive layer. The first dielectric layer is patterned to form a contiguous planar path substantially parallel to a top surface of the substrate. Patterning the first dielectric layer includes defining a dielectric region of the first dielectric layer surrounded by a portion of the contiguous planar path, and forming a first via hole in the dielectric region. The contiguous planar path and the via hole are filled with a conductive material. The conductive material in the contiguous planar path forms a second conductive layer, and the contiguous planar path extends from a first lateral side wall of the second conductive layer to a second lateral sidewall of the second conductive layer. A bond pad is formed over the second conductive layer, and the bond pad is electrically connected to the second conductive layer.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wei Chen, Hao-Yi Tsai, Yu-Wen Liu
  • Patent number: 9594282
    Abstract: In an active matrix substrate, each of a plurality of auxiliary capacitance electrodes contain a first electrode section and a second electrode section, at least a portion of the first electrode sections and at least a portion of a plurality of source bus lines overlap each other, the second electrode section has two linear sections that branch from the first electrode section and that extend in a second direction, a portion of the region between the two linear sections and at least a portion of the plurality of source bus lines overlap each other, and the first and second electrode sections, which are adjacent and arranged in a first direction, are disposed symmetrically to each other about a reference point that is on a straight line passing through a substantially central portion of respective pixels arranged in the first direction.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: March 14, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Ryohki Itoh, Masahiro Yoshida, Takaharu Yamada
  • Patent number: 9589872
    Abstract: An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of the control FETs and each of the sync FETs. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: March 7, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Dan Clavette
  • Patent number: 9590142
    Abstract: A light emitting diode including a magnetic structure and a method of fabricating the same are disclosed. The magnetic structure composed of passivation layers and a magnetic layer is disposed inside a luminous structure composed of an active layer and a semiconductor layer. In the light emitting diode, the magnetic structure including the magnetic layer is disposed on a side surface of the active layer to improve recombination rate of charge carriers for light emission by increasing influence of a magnetic field applied to the active layer. In addition, the light emitting diode according to the present invention allows change in position of the magnetic structure including the magnetic layer depending upon an etched shape of the luminous structure, thereby realizing various magnetic field distributions.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: March 7, 2017
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Seong-Ju Park, Youngchul Leem, Jae-Joon Kim
  • Patent number: 9589998
    Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 7, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Do-Hyun Kim, Yoon Ho Khang, Dong-Hoon Lee, Sang Ho Park, Se Hwan Yu, Cheol Kyu Kim, Yong-Su Lee, Sung Haeng Cho, Chong Sup Chang, Dong Jo Kim, Jung Kyu Lee
  • Patent number: 9589986
    Abstract: The invention provides an array substrate, a method therefor and a display device. The array substrate includes: a substrate, and a thin film transistor (TFT) and a pull-down capacitor disposed on the substrate. The TFT includes: a gate, a gate insulating layer, a channel layer, a source, a drain and a passivation layer. The passivation layer is disposed with a via hole corresponding to the drain, a pixel electrode is connected to the drain through the via hole. The pull-down capacitor includes: a first conductive layer, a first spacer layer, a filling layer, a second spacer layer and a second conductive layer successively stacked on the substrate. The sum of thicknesses of the filling layer and the first spacer layer is greater than the sum of thicknesses of the drain and the channel layer, to make the second conductive layer and the pixel electrode be located at different levels.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: March 7, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Huan Liu