Patents Examined by Ji H. Bae
  • Read clock generation circuit and data processing circuit including the same
    Patent number: 11275402
    Abstract: A read clock generation circuit may include a multiplexer selecting one of divided clock signals in response to a selection signal and outputting the selected divided clock signal as a preliminary read clock signal, a detection circuit generating a detection signal for indicating detection timing of a divided clock signal having the fastest second edge after the first edge of a write clock signal, among the divided clock signals, based on a result of a comparison between the phases of the divided clock signals and the phase of the write clock signal, a counter generating the selection signal by counting the detection signal in response to the write clock signal, and a correction circuit outputting, as a read clock signal, a signal from which pulses corresponding to an invalid section have been removed, among the pulses of the preliminary read clock signal, in response to the detection signal.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Minsoon Hwang
  • Power supply device for supplying power to server and power supply management system
    Patent number: 11249528
    Abstract: A power supply device for supplying power to a server and a power supply management system are provided. The device includes: a power supply control chip, a first connector, a voltage comparator, a counter and a resistance regulation circuit. The resistance regulation circuit includes a pull-up resistance circuit and a pull-down resistance circuit including multiple resistor branches and switches. An input terminal of the voltage comparator is connected to an address input terminal, the other input terminal of the voltage comparator is connected to a connection point of the resistance regulation circuit. An input terminal of the counter is connected to an output terminal of the voltage comparator, each output terminal of the counter is connected to one switch and controls a state of the switch. Each output terminal of the counter is connected to one address pin of the power supply control chip.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 15, 2022
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO LTD
    Inventor: Siheng Luo
  • USB type-C power delivery management
    Patent number: 11249537
    Abstract: When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Chee Lim Nge, Eugene Gorbatov, Zhongsheng Wang, James G. Hermerding, II, Basavaraj B. Astekar, Jenn Chuan Cheng, Chia-Hung Sophia Kuo, Ashwin Umapathy, Tin-Cheung Kung, Yifan Li, Alexander B. Uan-Zo-Li
  • System and method for controlling a power-on sequence and power throttling using power brake
    Patent number: 11243592
    Abstract: An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 8, 2022
    Assignee: Dell Products L.P.
    Inventors: Johan Rahardjo, Jeremiah James Bartlett, Joshua David Anderson, Isaac Qin Wang, Duk M. Kim
  • Set-top box reboot and polling tool
    Patent number: 11240562
    Abstract: A system and method for polling a plurality of client devices of different types are provided. A reboot and polling tool pre-polls client devices, where the pre-poll is specific to a type of client device and identifies a state of the client devices. The reboot and polling tool then executes a script on the client devices that changes the state of the plurality of client devices. After the script is executed, the reboot and polling tool post-polls the client devices where the post-poll is specific to the type of client device and the post-poll provides information that identifies changes in the state of the client devices caused by the script.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 1, 2022
    Assignee: CSC Holdings, LLC
    Inventor: Christopher Quinn
  • Power gating system and electronic system including the same
    Patent number: 11237619
    Abstract: A power gating system may include a logic circuit area configured to perform a power-down operation according to at least one power-down control signal. The power gating system may also include a power gating control circuit configured to generate the at least one power-down control signal when a power-down request period is equal to or greater than a preset time according to a power-down mode signal.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Clock recovery using between-interval timing error estimation
    Patent number: 11231740
    Abstract: Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: January 25, 2022
    Assignee: CREDO TECHNOLOGY GROUP LIMITED
    Inventors: Fang Cai, Junqing Sun, Haoli Qian
  • Controlling power state demotion in a processor
    Patent number: 11216276
    Abstract: In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Hisham Abu-Salah, Daniel Lederman, Nir Rosenzweig, Efraim Rotem, Esfir Natanzon, Yevgeni Sabin, Shay Levy
  • Providing access from outside a multicore processor SoC to individually configure voltages
    Patent number: 11216409
    Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Daniel J. Ragland, Guy M. Therien, Kirk Pfaender
  • Clock frequency adjustment for workload changes in integrated circuit devices
    Patent number: 11209886
    Abstract: Clock control arrangements for integrated circuit devices are discussed herein. In one example, a method of operating an integrated circuit device includes monitoring indications of pending operations for a processing core of an integrated circuit, and determining a predicted change in workload for the processing core based at least on a portion of the indications of the pending operations. The method also includes altering a clock frequency of a clock signal provided to the processing core based at least on the predicted change in the workload.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 28, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: William Paul Hovis, Andrew Benson Maki, Francine Mary Shammami
  • Storage system, method of controlling same, information processing apparatus, and storage medium
    Patent number: 11188139
    Abstract: A sub-CPU of a storage system discriminates in advance whether a storage device connected to a SATA bridge is an HDD (a first type) or an SSD (a second type). Upon receiving a power saving shift instruction that does not distinguish a type of the storage device from a main CPU via a SATA controller, the sub-CPU instructs a power control unit corresponding to the discriminated type to perform power control for causing the storage device to shift to a power saving state. The sub-CPU makes an instruction for power control to a GPIO if the discriminated type is HDD, and has a SATA host I/F cause the storage device shift to the power saving state if the discriminated type is SSD.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: November 30, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Minoru Hashimoto
  • Controlling operating voltage of a processor
    Patent number: 11175712
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Eyewear use detection
    Patent number: 11163155
    Abstract: Eyewear including a support structure defining a region for receiving a head of a user. The support structure supports optical elements, electronic components, and a use detector. The use detector is coupled to the electronic components and is positioned to identify when the head of the user is within the region defined by the support structure. The electronic components monitor the use detector and transition from a first mode of operation to a second mode of operation when the use detector senses the head of the user in the region.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 2, 2021
    Assignee: Snap Inc.
    Inventors: Julio Cesar Castañeda, Rajeev Ramanath
  • Optimizing host CPU usage based on virtual machine guest OS power and performance management
    Patent number: 11150933
    Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: October 19, 2021
    Assignee: VMware, Inc.
    Inventors: Andrei Warkentin, Cyprien Laplace, Regis Duchesne, Ye Li, Alexander Fainkichen
  • Apparatus, method, and storage medium for controlling a power saving state in a SATA storage system
    Patent number: 11144109
    Abstract: An information processing apparatus comprising a first controller, a second controller provided between the first controller and a storage device, and a main controller that sets a power saving state of the first controller, the second controller and the storage device. The first controller transitions to the power saving state in response to a transition request from the main controller, the second controller transitions to the power saving state in response to the power saving state to which the first controller has transitioned, and the first controller starts restoration processing from the power saving state in response to an interrupt from the main controller and determines, based on whether the second controller is performing power control on the storage device, whether to execute preprocessing which is accompanied by access to the storage device.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: October 12, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akihiro Matsumoto
  • Powering clock tree circuitry using internal voltages
    Patent number: 11132015
    Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenji Asaki, Shuichi Tsukada
  • Controlling a processor clock
    Patent number: 11119559
    Abstract: There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 14, 2021
    Assignee: GRAPHCORE LIMITED
    Inventors: Stephen Felix, Mrudula Gore
  • Modular embedded chassis with firmware for removably coupled compute devices, and methods and systems for the same
    Patent number: 11100230
    Abstract: In some embodiments, an apparatus can include a host board that has multiple connectors. Each connector from the multiple connectors removably connects to a unique compute device from multiple compute devices. The apparatus can further include a memory that stores a first firmware. The apparatus can further include a controller that is operatively coupled to the multiple connectors and the memory. The controller provides access to the first firmware by a compute device from the multiple compute devices when the compute device removably connects to the host board via a connector from the multiple connectors and when a circuit of the compute device disables access to the memory of the compute device to cause the compute device to continue a power-on cycle using the first firmware.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 24, 2021
    Assignee: Management Services Group, Inc.
    Inventor: Thomas S. Morgan
  • Apparatus for dynamic learning of voltage source capabilities
    Patent number: 11101736
    Abstract: A system may include a power supply configurable to generate any of a plurality of output voltages on a power supply output node. The system also may include a voltage auto-detection power distribution (PD) controller coupled to the power supply. The voltage auto-detection PD controller is configured to monitor an input signal for detection of presence of a device coupled to the system via a cable and assert combinations of a plurality of control signals. For each combination of control signals, the voltage auto-detection PD controller measures a value of an output voltage from the power supply, stores the measured value, and generates a plurality of packets for transmission to the device. Each packet contains a parameter indicative of a measured output voltage.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 24, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Deric Wayne Waters
  • System and method for power management of a computing system with a plurality of islands
    Patent number: 11068018
    Abstract: The invention concerns a computing system comprising: an island (102) comprising a group of circuits capable of operating in one of a plurality of operating modes, the island being coupled to an island control circuit (122); and a clock generation circuit (902) supplying a further clock signal to the island control circuit (122) for controlling a change of mode of the island, the clock generation circuit (902) being configured to select one of a plurality of clock frequencies for the further clock signal, the selection being based on the change of operating mode to be applied.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 20, 2021
    Assignee: Dolphin Design
    Inventors: Mathieu Louvat, Lionel Jure, Gauthier Reveret, Alexandre Charvier