Abstract: Examples described herein include systems and methods for retaining information about bad memory pages across an operating system reboot. An example method includes detecting, by a first instance of an operating system, an error in a memory page of a non-transitory storage medium of a computing device executing the operating system. The operating system can tag the memory page as a bad memory page, indicating that the memory page should not be used by the operating system. The operating system can also store tag information indicating memory pages of the storage medium that are tagged as bad memory pages. The example method can also include receiving an instruction to reboot the operating system, booting a second instance of the operating system, and providing the tag information to the second instance of the operating system. The operating system can use the tag information to avoid using the bad memory pages.

Abstract: Systems and methods are provided for powering an Information Handling System (IHS). The system includes a multimode AC adapter that reports supported outputs, including USB-PD (Universal Serial Bus Power Delivery) outputs and also including high-power outputs of a voltage greater than the USB-PD output voltages. The IHS detects a coupling of the multimode AC adapter to a USB-C port of the IHS. Based on information provided by the multimode adapter, the IHS determines the multimode adapter supports transmission of the high-power outputs to the USB-C port. The high-power outputs are negotiated and a power circuit of the IHS is configured for converting the negotiated high-power output. The configured power circuit converts the negotiated high-power output received via the USB-C port to an input utilized by the IHS. The high-power conversion circuit may provide efficient conversion of input voltages of up to 60 volts to voltages for use by the IHS.

Abstract: Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential FS/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

Abstract: An electronic device is provided. The electronic device includes an operation of determining at least one control level by executing at least one scheduling process, an operation of selecting one control level from among the at least one control level, and an operation of transmitting a power control signal corresponding to the selected control level to one or more control target devices. The operation of determining the control level may include an operation of performing a first scheduling process of receiving first power usage data from an external power amount data providing device and determining a first control level based on the first power usage data. In addition to this, various embodiments identified through the specification are possible.

Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

Abstract: In some examples, an embedded controller of a computing device may detect, when the computing device is in a low-power state, that a smartcard has been connected to a port of the computing device or that data has been received from an input device (e.g., keyboard or biometric input device) connected to the computing device. For the smartcard, the embedded controller may use a card driver to read data stored on the smartcard. The embedded controller may compute a hash value based on the data read from the smartcard or received from the input device. If the hash value matches a previously stored hash value, then the embedded controller may initiate a boot-up process of the computing device. If the hash value does not match the previously stored hash value, then the embedded controller may cause the computing device to remain in the low-power state.

Abstract: A pulse counting apparatus operating at a low power and an operation method thereof are provided. The pulse counting apparatus includes a pulse counter configured to count a number of pulses inputted from outside of the pulse counting apparatus and generate an interrupt signal; a timer unit configured to generate a wake-up signal according to a preset time; a real time clock (RTC) configured to serve as a clock of the pulse counter and the timer unit; and a processor configured to switch from a sleep mode to an active mode when the interrupt signal or the wake-up signal is generated.

Abstract: A line module for use in a network device includes a plurality of circuits; and a power module connected to the plurality of circuits, and to a first Power Distribution Unit (PDU) and a second PDU, wherein the first PDU and the second PDU provide power distribution by different feeds, wherein the power module is configured to initiate a shutdown procedure when one or more of i) a current drawn from any feed equals or exceeds a first current threshold, and ii) an aggregate current drawn from all feeds equal or exceeds a second current threshold.

Abstract: An image processing apparatus includes a connection unit, a first power supply unit, a second power supply unit, and a control device. The connection unit is connected to an electronic apparatus including a controlled device and a communication relay unit. The first power supply unit can supply power to the controlled device. The second power supply unit can supply power to the communication relay unit. The control device is capable of switching a power supply state by the first power supply unit and the second power supply unit between at least a first stop state in which power supply by the first power supply unit is continued and power supply by the second power supply unit is stopped and a second stop state in which power supply by the first power supply unit and the second power supply unit is stopped.

Abstract: An electronic apparatus and a power management method thereof are provided. The power management method is adapted to the electronic apparatus and includes the following steps. A target time is obtained according to a user input. A remaining demand time is determined according to the target time and an elapsed time after activating timing. A time-to-empty of a battery device is obtained. The time-to-empty of the battery device and the remaining demand time are compared to provide a visual notification and a user behavior suggestion message according to the comparison result. The user behavior suggestion message includes at least one power saving operation.

Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.

Abstract: Systems and methods for operating a power source as a heating device in an Information Handling System (IHS) are described. In some embodiments, an IHS may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive an indication to increase a temperature of the IHS and, in response to the indication, concurrently set a first power supply in source mode and a second power supply in sink mode.

Abstract: A universal serial bus (USB) source device adapted to be coupled to a USB sink device via a USB cable, the USB source device including: a voltage bus (VBUS) terminal adapted to be coupled to a VBUS conductor of the USB cable; a configuration channel (CC) terminal adapted to be coupled to a CC conductor of the USB cable; a VOUT node coupled to the VBUS terminal and adapted to be coupled to a voltage supply; a controller circuit coupled to the VBUS terminal, the CC terminal and the VOUT node; a load circuit coupled to a discharge signal connection of the controller and to the VOUT node; and a resistor divider coupled to the VOUT node and the controller and adapted to be coupled to the voltage supply.

Abstract: Provided is an information processing apparatus that performs alteration detection processing on every occasion of starting a program, comprising a writing component capable of writing a setting indicating whether or not to perform the alteration detection processing to a first region referable by a first program that firstly performs the alteration detection processing on another program and to a second region not referable by the first program at a point when the first program is started. The first program performs the alteration detection processing in accordance with the setting written in the first region, and a second program capable of referring to the second region performs the alteration detection processing in accordance with the setting written in the second region.

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Abstract: A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

Abstract: Provided are a communication system, a communication device, and a power saving method, which enable a communication partner device to reliably recognize a communication unit switched to an ON state in response to reception of a predetermined signal from the communication partner device. A BLE chip transmits a BLE BD address when a BT3 chip is in an OFF state. A mobile terminal identifies a BT3 BD address associated with the BLE BD address received from a BLE chip based on stored correspondence data. A card reader switches the state of the BT3 chip to an ON state when the BLE chip receives a predetermined signal transmitted from the mobile terminal. The BT3 chip switched to an ON state starts to communicate data to be used for predetermined information processing to and from the mobile terminal.

Abstract: The disclosure provides a restart control device and a restart control method. The restart control device is disposed in an electronic device. The electronic device includes a keyboard and a restart button. At least one assigned key of a plurality of keys of the keyboard is set. The restart control device determines whether the at least one assigned key is pressed, and determines whether the restart button is pressed. When determining that the restart button is pressed and the at least one assigned key is pressed, the restart control device provides a restart control signal to cause the electronic device to perform a restart operation. The disclosure can prevent an unnecessary restart operation due to a single restart button being mistyped.