Patents Examined by John D. Smith
  • Patent number: 4618509
    Abstract: A process is disclosed for preparing novel arrays of metal coordination compounds characterized by arrangement of the metal ions, separated by a linking agent, in stacked order one above the other. The process permits great flexibility in the design of the array. For example, layers of different composition can be added to the array at will.
    Type: Grant
    Filed: May 29, 1984
    Date of Patent: October 21, 1986
    Assignee: University of Delaware
    Inventor: John E. Bulkowski
  • Patent number: 4618510
    Abstract: A method of fabricating sub-micrometer gates in a semiconductor device is disclosed in which a pre-passivation layer is formed over the gate region during fabrication. This pre-passivation layer protects the gate and underlying gate trough region from surface contamination during device fabrication. Sub-micrometer gate lengths are obtained by use of optical lithography, e.g., angle-shadow metal evaporation techniques and chemical lift-off methods.
    Type: Grant
    Filed: September 5, 1984
    Date of Patent: October 21, 1986
    Assignee: Hewlett Packard Company
    Inventor: Tun S. Tan
  • Patent number: 4617206
    Abstract: Providing a transparent layer of an oxide of an element from group IVa of the Periodic Table, notably TiO.sub.2, by providing a substrate with a solution of a compound of the element which upon heating is converted into the relevant oxide, drying the film and heating the dried film so as to form the transparent layer of the oxide. The oxide thus obtained is a form having a comparatively low refractive index. By heating the product, after providing the film, rapidly to a temperature of above 700.degree. C., preferably above 1,000.degree. C., keeping it at this temperature for some time and then rapidly cooling it again, a modification having a higher refractive index (for example, for TiO.sub.2 rutile) is obtained.
    Type: Grant
    Filed: August 30, 1984
    Date of Patent: October 14, 1986
    Assignee: U.S. Philips Corporation
    Inventors: Jan Haisma, Petrus Heller, Johannes M. M. Pasmans, Udo K. P. Biermann
  • Patent number: 4617195
    Abstract: A method for forming electroluminescent devices is disclosed. A first conductor is deposited on a substrate in a preselected pattern so as to form a first electrode. A first portion of the first conductor is then covered with a luminescent coating. A pair of second conductors are then deposited adjacent to each other, one of the second conductors forming a second electrode and contacting only the luminescent coating and the substrate, while the other second conductor contacts only the first conductor and the substrate. An insulative film is then deposited so as to cover the pair of second conductors. A conductive shielding layer is then deposited over the insulating film. The shielding layer includes a terminal portion adapted to be connected to a suitable ground.
    Type: Grant
    Filed: August 27, 1984
    Date of Patent: October 14, 1986
    Assignee: Microlite, Inc.
    Inventor: Richard W. Mental
  • Patent number: 4616597
    Abstract: An improved radio frequency (RF) glow discharge apparatus is disclosed for depositing dielectric films onto substrates in a continuous operation. The apparatus includes one or more capacitively coupled electrodes, with a plate of a dielectric material that overlies the surface of the electrode(s) coupled with the plasma. The thickness of the plate is sufficient such that during deposition with the apparatus of this invention, the amount of material deposited on the electrodes is negligible, and the potential between the electrodes and the substrate remains substantially the same. This, in turn, insures that the chemical structure and properties of the deposited films are reproducible over long periods of operation.
    Type: Grant
    Filed: October 31, 1984
    Date of Patent: October 14, 1986
    Assignee: RCA Corporation
    Inventor: Grzegorz Kaganowicz
  • Patent number: 4617204
    Abstract: Processes for (1) depositing main group metals on inorganic and metallic substrates, (2) depositing transition metals on organic, inorganic and metallic substrates, and (3) depositing combinations of main group metals and transition metals on organic, inorganic and metallic substrates. The resulting products have useful electrical, optical and/or decorative properties.
    Type: Grant
    Filed: June 28, 1985
    Date of Patent: October 14, 1986
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventor: Robert C. Haushalter
  • Patent number: 4615913
    Abstract: This invention discloses a means of producing chromium oxide bonded coatings applied to metal or other suitable substrates in a layered, built-up manner and the products produced thereby.
    Type: Grant
    Filed: March 13, 1984
    Date of Patent: October 7, 1986
    Assignee: Kaman Sciences Corporation
    Inventors: Jack L. Jones, Kenneth M. Chidester
  • Patent number: 4615766
    Abstract: A method of manufacturing GaAs semiconductor devices includes the steps of emplacing doping impurities by ion implantation on at least one surface of a GaAs substrate, and a step of annealing to remove damage resulting from the implantation of the impurities in the GaAs material. Prior to the annealing, a silicon capping layer is deposited on the surface by either sputtering, evaporation, or vapor deposition to a thickness of 100-10,000 angstroms. Subsequent to the annealing, the silicon capping layer is removed by etching. The silicon cap prevents out-diffusion of arsenic from the GaAs, and has a coefficient of thermal expansion which is sufficiently close to that of the GaAs to inhibit the formation of cracks in the capping layer.
    Type: Grant
    Filed: February 27, 1985
    Date of Patent: October 7, 1986
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Jackson, Gwen Pepper, Richard F. Rutz
  • Patent number: 4615909
    Abstract: A number of wafer slices of semiconductor material are heated in a reactor tube arranged inside a furnace tube with the reactor tube having openings through which a reaction gas is passed for depositing semiconductor material on the wafer slices. This is effected by producing in the furnace tube a flow of reaction gas along the outer side walls of the reactor tube and by passing only a part of this flow through the openings into the reactor tube. By using this method, particles of large size and different composition, which may be formed in the reaction gas, are prevented from being deposited on the wafer slices.
    Type: Grant
    Filed: April 15, 1985
    Date of Patent: October 7, 1986
    Assignee: U.S. Philips Corporation
    Inventors: Henri J. Thijssen, Antonius J. M. Uijen, Paulus Z. A. M. Van der Putte
  • Patent number: 4614666
    Abstract: Improved silicon semi-conductor device and process includes three layer sandwich passivation coating. The sandwich coating comprises first, a thin silica layer, preferably produced by oxidizing a silicon surface to the minimum thickness necessary to prevent interdiffusion of an overlying nitride layer with the silicon subsurface. The second layer of the sandwich construction is nitride and the third layer is a thicker layer of silica, preferably produced by plasma glass deposition which, together with the inner silica layer provides preselected electrical characteristics required of the composite barrier or passivation coating. This invention reduces manufacturing defects produced in conventional two layer passivation coatings, including a thicker silica inner layer, due to undercutting of the thicker silica inner layer upon etching to form terminal areas. Such undercutting is avoided by the thin silica inner layer in the present invention.
    Type: Grant
    Filed: February 7, 1985
    Date of Patent: September 30, 1986
    Assignee: Sperry Corporation
    Inventor: Timothy M. Lindenfelser
  • Patent number: 4612207
    Abstract: Disclosed is an apparatus for affecting the preparation of thin film transistor arrays comprised of a chamber means with a gas inlet means, and a gas exhaust means, first rotatable polygon electrode means, second stationary counterelectrode means of cylindrical shape situated coaxially with the first electrode means, and substrate means to be coated present on the first polygon electrode means.
    Type: Grant
    Filed: January 14, 1985
    Date of Patent: September 16, 1986
    Assignee: Xerox Corporation
    Inventor: Frank Jansen
  • Patent number: 4612249
    Abstract: A process of bonding a coating of a polyurethane resin to a polyolefin substrate is provided. The polyolefin substrate is coated with a graft copolymer of a polyolefin and a functional monomer such as acrylic acid. The graft copolymer is flame treated to fuse it. A liquid polyurethane precursor composition is then applied thereto and cured.
    Type: Grant
    Filed: December 21, 1984
    Date of Patent: September 16, 1986
    Assignee: RCA Corporation
    Inventors: Marvin Packer, John X. Fritz
  • Patent number: 4611554
    Abstract: A device and method for the treatment of printed circuit boards with process solutions, in which the boards being treated are continually vertically moved by a transporting conveyer above an accumulating reservoir and below spraying nozzles which apply a process solution to the side surfaces of each board. Two collecting receivers are arranged in mirror-inverted relationship at two sides of the boards being treated. The reservoir, into which the process solution drains from the receivers and the boards, is connected to the spraying nozzles by tubular conduits, provided with regulating valves, in a closed circuit, whereby the accumulated solution is fed back to the nozzles.
    Type: Grant
    Filed: January 24, 1985
    Date of Patent: September 16, 1986
    Assignee: Schering Aktiengesellschaft
    Inventors: Hartmut Mahlkow, Horst Blasing
  • Patent number: 4610910
    Abstract: A printed circuit board comprising an insulating board deposited with a catalyst having reactivity against electroless plating deposition, a resist for electroless plating provided on the insulating board excepting the part where a circuit is to be formed and a circuit formed by electroless plating, wherein the resist for electroless plating contains a coupling agent having a function of preventing the catalyst from ionizing. A process for producing the printed circuit board in which the insulating board surface excepting the part where a circuit is to be formed is covered with a resist for electroless plating containing a coupling agent having a function of preventing the catalyst from ionizing. Use of said resist for electroless plating can prevent drop of insulation resistance of the insulating board after moisture absorption.
    Type: Grant
    Filed: September 28, 1984
    Date of Patent: September 9, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Mineo Kawamoto, Kanji Murakami, Haruo Akahoshi, Yoichi Matsuda, Motoyo Wajima, Makoto Matsunaga, Shoji Kawakubo, Toyofusa Yoshimura, Haruo Suzuki, Tomio Yoshida
  • Patent number: 4608941
    Abstract: Apparatus for soldering printed circuit panels includes a roll configuration to convey the panels horizontally across a container carrying molten solder. The printed circuit panels are immersed in molten solder when they pass through the roll configuration. At least one air knife located at the output side of the roll configuration serves to level the molten solder on the panels as they exit from the rolls.
    Type: Grant
    Filed: January 10, 1985
    Date of Patent: September 2, 1986
    Assignee: Teledyne Electro-Mechanisms
    Inventor: Gilbert V. Morris
  • Patent number: 4609568
    Abstract: A process for fabricating self-aligned regions of metal silicide on bipolar integrated circuits having self-aligned polycrystalline silicon emitters and base contacts includes the steps of depositing a layer of polycrystalline silicon across the surface of the structure, patterning the polycrystalline silicon to define the emitters and base contacts as well as resistors and diodes, heating the structure to transfer desired conductivity dopants from the polycrystalline silicon into the underlying structure, forming a protective layer over those regions of the structure where metal silicide is not desired, depositing a layer of refractory metal across the entire structure, and reacting the refractory metal with the underlying silicon to form metal silicide.
    Type: Grant
    Filed: July 27, 1984
    Date of Patent: September 2, 1986
    Assignee: Fairchild Camera & Instrument Corporation
    Inventors: Yun Bai Koh, Frank Chien, Madhu Vora
  • Patent number: 4608275
    Abstract: A method of electroless deposition of metal on a non-conductive substrate is disclosed and comprises treating a substrate prior to electroless deposition with a catalyst composition containing a mixed tin-palladium catalyst. An improvement in metal deposition is obtained by contacting the treated substrate with an alkaline accelerator bath containing an agent which oxidizes the tin.
    Type: Grant
    Filed: March 18, 1985
    Date of Patent: August 26, 1986
    Assignee: MacDermid, Incorporated
    Inventors: Peter E. Kukanskis, John J. Grunwald, David Sawoska
  • Patent number: 4606936
    Abstract: Stress is eliminated between a dielectrically passivated silicon wafer and a thick polycrystalline silicon layer by depositing a low melting transition layer such as a doped silica glass over the passivated silicon wafer.
    Type: Grant
    Filed: April 12, 1985
    Date of Patent: August 19, 1986
    Assignee: Harris Corporation
    Inventors: George Bajor, Charles Messmer
  • Patent number: 4606935
    Abstract: High purity oxidation is produced on a semiconductor substrate. The process includes heating the semiconductor substrate in the presence of an oxidizing ambient in a multi-walled reaction chamber containing a heating element. A halogen-containing ambient flows in an outer portion of the reaction chamber intermediate between the inner portion and the heating element to react with heating element contaminant. In a portion of the reaction chamber position intermediate of the inner portion and the outer portion, a gaseous ambient flows to remove water by-product from the reaction with the halogen which occurs in the outer portion of the reaction chamber. The apparatus for carrying out the above process is also provided.
    Type: Grant
    Filed: October 10, 1985
    Date of Patent: August 19, 1986
    Assignee: International Business Machines Corporation
    Inventor: Samuel E. Blum
  • Patent number: 4606927
    Abstract: A minute color coded identifier having a longitudinal axis, which is transversely color banded about its periphery. The identifier may, for example, be 0.015 inch long, have a transverse dimension of about 0.004 inch and have seven or more color bands such as to be observable under a power of 10 or more magnification. A method of making such identifiers, as well as a method of applying the same to articles for later identification is disclosed that involves a dispersion of identifiers in a transparent and hardenable cementitious liquid such as nitrocellulose in a suitable volatile solvent such as acetone and ethyl acetate, e.g. a common clear fingernail polish.
    Type: Grant
    Filed: August 10, 1983
    Date of Patent: August 19, 1986
    Inventor: Ronald L. Jones