Abstract: A lateral insulated gate turn-off device includes an n-drift layer, a p-well formed in the n? drift layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, a trenched first gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, an anode electrode electrically contacting the p+ type anode region, and a trenched second gate extending from the p+ type anode region into the n-drift layer. For turning the device on, a positive voltage is applied to the first gate the reduce the base width of the npn transistor, and a negative voltage is applied to the second gate to effectively extend the p+ emitter of the pnp transistor further into the n-drift layer to improve performance.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? drift layer, a p-well, trenched insulated gates formed in the p-well, and n+ regions between at least some of the gates, so that vertical npn and pnp transistors are formed. A cathode electrode is on top, and an anode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the cathode electrode. To direct high energy electrons away from a gate oxide layer on the sidewalls of the trenches, boron is implanted between the trenches so p+ regions are formed in the mesas of the less-doped p-well. The p+ regions break down during an over-voltage event before the p-well breaks down in the mesas.

Abstract: A semiconductor package includes a first die and a second die. The first die includes a first spiral section and first bonding metallurgies of an inductor. The first bonding metallurgies are connected to the first spiral section. The second die is bonded to the first die. The second die includes a second spiral section and second bonding metallurgies of the inductor. The second bonding metallurgies are connected to the second spiral section. The inductor extends from the first die to the second die.

Abstract: An insulated gate bipolar transistor includes: a semiconductor substrate; an emitter electrode arranged on one main surface of the semiconductor substrate; and a trench gate arranged in a rectangular trench having a rectangular shape and disposed on the one main surface of the semiconductor substrate. The semiconductor substrate includes a body contact region and an emitter region in a rectangular region surrounded by the rectangular trench. The rectangular trench has a straight trench that constitutes one side of the rectangular trench. The body contact region is in contact with a side of the straight trench. The emitter region is in contact with the side of the straight trench, and is adjacent to the body contact region. The body contact region has a protrusion portion protruding in a depth direction from a center portion of the body contact region.

Abstract: A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.

Abstract: Provided is an integrated circuit structure and a method for manufacturing the same. The integrated circuit structure comprises a substrate; a plurality of interconnecting structures on the substrate, each of the interconnecting structures comprises side surfaces and a top surface, the side surfaces directly define air gaps therebetween isolating the interconnecting structures from each other; and a planar protective layer on top of the plurality of interconnecting structures covering all of the air gaps. The protective layer comprises a sheltering film and a supporting film.

Abstract: A light emitting device including a base, a first electrode, a barrier structure layer, a light emitting layer and a second electrode is provided. The barrier structure layer includes a first barrier layer in contact with the first electrode, a second barrier layer and a third barrier layer. The first barrier layer, the second barrier layer and the third barrier layer stack sequentially. The materials of the first barrier layer and the third barrier layer include a dielectric material. The material of the second barrier layer includes a metal material. A boundary between the third barrier layer and the second barrier layer keeps a vertical distance from the first electrode. The light emitting structure layer is disposed between the first electrode and the second electrode and surrounded by the barrier structure layer. The thickness of the light emitting structure layer is not greater than the vertical distance.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.

Abstract: A display panel, a method for fabricating the same, and a display device are disclosed, where the display panel includes: a base substrate, sub-pixel units in at least two colors on the base substrate, and an anti-reflection layer on a side of the sub-pixel units away from the base substrate, wherein the anti-reflection layer includes anti-reflection components arranged in an array, which correspond to the sub-pixel units in a one-to-one manner, and are configured to alleviate reflected light in the same colors as the corresponding sub-pixel units, and sub-pixel units in different colors correspond to different anti-reflection components.

Abstract: A semiconductor device that includes active patterns defined in a substrate, and gate patterns extending in a first direction while traversing the active patterns. First wiring line patterns disposed over a first dielectric layer which covers the gate patterns, and extending in the first direction. The first wiring line patterns comprise internal wiring line patterns coupled with first vertical vias, which pass through the first dielectric layer and are coupled to the active patterns and the gate patterns, and power routing patterns not coupled with the first vertical vias. The first wiring line patterns are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting with the first direction, and the first active patterns are disposed between the power routing patterns when viewed on a top.

Abstract: An insulated gate bipolar transistor (IGBT) device and a method for manufacturing the same are provided. The present disclosure relates to power semiconductor devices. In order to relieve the problem of wafer warping caused by trench stress in an IGBT manufacturing process without affecting other performance parameters of the IGBT, it provides the following technical solution: optimizing the design of arrangement densities and arrangement regions of device trenches. The present disclosure can alleviate the problem of wafer warping caused by trench stress in the IGBT manufacturing process, improve the product yield of IGBT chips, and enhance the latch-up immunity of the IGBT, so that the IGBT is more robust and durable.

Abstract: An interconnect structure is provided. The interconnect structure includes a first metallization layer, an insulating layer and a second metallization layer. The first metallization layer includes, at an uppermost surface thereof, a first body formed of first dielectric material, first metallic elements and buffer elements formed of second dielectric material adjacent the first metallic elements. The insulating layer is disposed on the uppermost surface of the first metallization layer and defines apertures located at the first metallic elements and the corresponding buffer elements. The second metallization layer is disposed on the insulating layer and includes a second body formed of first dielectric material and second metallic elements located at the apertures and extending through the apertures to contact the corresponding first metallic elements and the corresponding buffer elements.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.

Abstract: The present invention provides a color conversion layer, a manufacturing method of the color conversion layer, and a display panel. The color conversion layer is used in a display panel having a direct surface light source. The color conversion layer includes a quantum dot film and a functional film. The functional film is arranged at one side of the quantum dot film facing the direct surface light source. A light wave emitted by the direct surface light source is transmitted through the functional film into the quantum dot film. A light wave excited by the quantum dot film is reflected into the quantum dot film through the functional film.

Abstract: Disclosed are an organic light emitting display device and a method for manufacturing a cover window thereof. The organic light emitting display device includes a display panel configured to display an image, and a cover window located above the display panel. The cover window includes a light path control structure configured to adjust a range of visibility of the image displayed by the display panel and to prevent occurrence of ghost mura.

Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

Abstract: A semiconductor device according to an embodiment comprises a semiconductor substrate having a through hole from a first face to a second face on an opposite side to the first face. A metal part is provided inside the through hole. A stacked film is provided between the metal part and an inner side surface of the through hole, and comprises a plurality of different material films of two or more types having a relative permittivity equal to or lower than 6.5.

Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer in the active region.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

Abstract: A semiconductor device includes a first electrode and a first carbon layer on the first electrode. A switch layer is disposed on the first carbon layer and a second carbon layer is disposed on the switch layer. At least one tunneling oxide layer is disposed between the first carbon layer and the second carbon layer. The device further includes a second electrode on the second carbon layer.