Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A method for determining spatial distribution of proppant incudes using signals detected by seismic sensors disposed proximate a formation treated by pumping fracturing fluid containing the proppant. Origin time and spatial position of seismic events induced by pumping the fracturing fluid are determined. Volume and orientation of at least one fracture in the subsurface formation associated with each induced seismic event are determined. Spatial distribution of a volume of the pumped fracturing fluid is determined using the volume and orientation of each fracture. A length of ellipsoidal axes is selected using a surface defined by a selected fractional amount of the total volume of frac fluid pumped into the formation. Spatial distribution of the proppant is determined using proppant mass, specific gravity and expected proppant porosity in the fractures, and spatially distributing a volume of the fractures within an ellipsoid defined by the ellipsoidal axes.

Abstract: A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract: Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.

Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

Abstract: Apparatuses, methods and systems apparatus for sensing an orientation are disclosed. One apparatus includes an accelerometer, wherein the accelerometer generates a sensed acceleration of the accelerometer and a gyroscope, wherein the gyroscope generates a sensed orientation of the gyroscope. The apparatus further includes a first adaptive filter, the first adaptive filter operative to receive at least the sensed acceleration and the sensed orientation of the gyroscope, and generate a first orientation (Q) of the apparatus, a second adaptive filter, the second adaptive filter operative to receive at least the sensed acceleration and the sensed orientation of the gyroscope, and generate a second orientation (Q?) of the apparatus, wherein a tuning for the first adaptive filter is different than a tuning for the second adaptive filter.

Abstract: In a method for fabricating a field-effect transistor (FET) structure, forming a shallow trench isolation (STI) structure on a semiconductor substrate, wherein the STI structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (ART) trenches. The method further includes epitaxially growing a first semiconductor material on the semiconductor substrate and substantially filling at least one of the one or more ART trenches, and recessing the first semiconductor material down into the ART trenches selective to the dielectric structures, such that the upper surface of the first semiconductor material is below the upper surface of the dielectric structures.

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

Abstract: A compound of the embodiment includes the structure represented by the following general formula (1). In the general formula (1), R1 to R4 respectively independently represent a hydrogen atom, a linear or branched alkyl group, a fluoroalkyl group, or an aryl group.

Abstract: A method embodiment includes providing a MEMS wafer comprising an oxide layer, a MEMS substrate, a polysilicon layer. A carrier wafer comprising a first cavity formed using isotropic etching is bonded to the MEMS, wherein the first cavity is aligned with an exposed first portion of the polysilicon layer. The MEMS substrate is patterned, and portions of the sacrificial oxide layer are removed to form a first and second MEMS structure. A cap wafer including a second cavity is bonded to the MEMS wafer, wherein the bonding creates a first sealed cavity including the second cavity aligned to the first MEMS structure, and wherein the second MEMS structure is disposed between a second portion of the polysilicon layer and the cap wafer. Portions of the carrier wafer are removed so that first cavity acts as a channel to ambient pressure for the first MEMS structure.

Abstract: A light-emitting device comprises a substrate having a top surface and a plurality of patterned units protruding from the top surface; and a light-emitting stack formed on the substrate and having an active layer with a first surface substantially parallel to the top surface, wherein one of the plurality of patterned units comprises a plurality of connecting sides constituting a polygon shape in a top view of the light-emitting device, the one of the plurality of patterned units comprises a vertex and a plurality of inclined surfaces respectively extending from the plurality of connecting sides, the plurality of inclined surfaces commonly join at the vertex in a cross-sectional view of the light-emitting device, the vertex being between the top surface of the substrate and the first surface of the active layer, and six of the plurality of patterned units forms a hexagon in the top view of the light-emitting device.

Abstract: High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed.

Abstract: Disclosed are a light emitting device, a method of manufacturing a light emitting device, a light emitting device package and a lighting system.

Abstract: A light-emitting element, a bonding layer, and a frame-like partition are formed over a substrate. The partition is provided to surround the bonding layer and the light-emitting element, with a gap left between the partition and the bonding layer. A pair of substrates overlap with each other under a reduced-pressure atmosphere and then exposed to an air atmosphere or a pressurized atmosphere, whereby the reduced-pressure state of a space surrounded by the pair of substrates and the partition is maintained and atmospheric pressure is applied to the pair of substrates. Alternatively, a light-emitting element and a bonding layer are formed over a substrate. A pair of substrates overlap with each other, and then, pressure is applied to the bonding layer with the use of a member having a projection before or at the same time as curing of the bonding layer.

Abstract: An organic light emitting display apparatus includes a base substrate, an active pattern disposed on the base substrate, a data line disposed on the base substrate, and a driving voltage line disposed on the base substrate. The active pattern includes a first transistor including a source area, a drain area and a channel. The active pattern also includes a first capacitor area and a second capacitor area. The data line extends in a first direction. The data line is overlapped with the first capacitor area. The driving voltage line extends in a second direction substantially perpendicular to the first direction. The driving voltage line is overlapped with the second capacitor area.

Abstract: A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat area, and the flat area extends in the second direction and the third direction.

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract: A method for displaying a terminal charging status and a terminal. The method includes: displaying a charging status region on a terminal screen when it is detected that a terminal battery is being charged, with a halo enlarging or shrinking with a preset frequency existing at the edge of the charging status region; according to a ratio of the current electric quantity of the terminal battery to the electric quantity of the terminal battery being fully charged, displaying a filled region having the same ratio in the charging status region. The method for displaying a terminal charging status and the terminal can realize visually displaying a charging status and a charging progress of the terminal.