Abstract: In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

Abstract: Provided are a substrate for an organic electronic device (OED) and a use thereof. The substrate may have excellent interfacial cohesive property by preventing interlayer delamination between the organic material layer and the inorganic material layer when being applied to manufacture a flexible device including a structure in which an organic material layer and an inorganic material layer are present together. In addition, when the substrate for an OED is used, an OED may have excellent durability and an excellent another required physical property such as light extraction efficiency.

Abstract: The present disclosure provides a packaging method with films, a film package structure and a display device, which can effectively prevent water and oxygen from invading into a display unit and improve the bending resistance of the display unit. The method comprises: step 1, placing an device to be packaged in a PECVD device, and setting a mask plate to expose a packaging region of the device and mask a region of the device that does not need to be packaged; step 2, adjusting a gas that is passed into the PECVD device, and depositing a layer of inorganic silicon material film; step 3, adjusting N2 gas that is passed into the PECVD device, and depositing a layer of organosilane film on the layer of the inorganic silicon material film using an organic material that reacts with the inorganic silicon material.

Abstract: The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.

Abstract: Provided is an organic light emitting diode display including a substrate; a display unit formed on the substrate and including a thin film transistor and an organic light emitting diode; a thin film encapsulation covering and encapsulating the display unit and formed by a laminated structure made of at least one first inorganic layer, a first organic layer, and a second inorganic layer; and a protective bezel fixed to the substrate and spaced apart from the side of the substrate to surround edges of the substrate and the thin film encapsulation.

Abstract: Provided are an organic electronic device (OED) and a use thereof. The OED, for example, a flexible device, may have excellent light extraction efficiency and durability. The OED may be applied to a lighting device or a light source for a display.

Abstract: A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

Abstract: A chip package and a method for forming the same are provided. The method includes: providing a first chip, wherein the first chip comprises a first surface and a second surface, and a first plurality of pads are disposed on the first surface; providing a second chip, wherein the second chip comprises a third surface and a fourth surface, a second plurality of pads are disposed on the third surface; combining the second surface of the first chip and the third surface of the second chip, wherein the second plurality of pads are out of the combination area of the first chip and the second chip; and forming a first insulation layer, wherein the first insulation layer covers the first chip, and is combined with the second chip. Processes of the method are simple, and the chip package is small.

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

Abstract: The present invention relates to an organic light emitting device and a method of preparing the same. More particularly, the organic light emitting device according to the present invention includes: a substrate; an organic light emitting unit in which a first electrode, an organic material layer, and a second electrode are sequentially stacked on the substrate; and an encapsulating unit configured to seal an external side of the organic light emitting unit, in which a protecting unit is provided on at least a partial region of the substrate, on which the organic light emitting unit and the encapsulating unit are not provided, and at least a partial region in a lateral surface region of the substrate.

Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

Abstract: An organic light emitting display device includes a substrate extending along a first direction, the substrate comprising a pixel region having a plurality of pixels and a transparent region that is located adjacent to the pixel region, a lower electrode disposed on the substrate in the pixel region, the lower electrode extending along the first direction, a light emitting layer disposed on the lower electrode, the light emitting layer extending along the first direction, and an upper electrode disposed on the light emitting layer in the pixel region, the upper electrode extending along the first direction. The upper electrode exposes the transparent region.

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

Abstract: A composition comprising: a first monomer comprising at least three thiol groups, each located at a terminal end of the first monomer, wherein the first monomer is represented by the following Chemical Formula 1-1: a second monomer comprising at least two unsaturated carbon-carbon bonds, each located at a terminal end of the second monomer, wherein the second monomer is represented by the following Chemical Formula 2: wherein in Chemical Formulae 1 and 2 groups R2, Ra to Rd, Ya to Yd, L1? and L2, X and variables k3 and k4 are the same as described in the specification, and a first light emitting particle, wherein the first light emitting particle consists of a semiconductor nanocrystal comprising a Group II-VI compound, a Group III-V compound, a Group IV-VI compound, or a combination thereof, wherein the first light emitting particle has a core/shell structure having a first semiconductor nanocrystal being surrounded by a second semiconductor nanocrystal, and the first semiconductor nanocrystal bei

Abstract: The present invention provides an OLED display substrate and a manufacture method thereof. The OLED display substrate comprises a substrate (10), a TFT (90) located on the substrate (10), a passivation layer (50) located on the TFT (90), a flat layer (60) located on the passivation layer (50), a connecting electrode (80) being located on the flat layer (60) and contacting the TFT (90), an anode (70) being located on the flat layer (60) and covering the connecting electrode (80), an organic emitting layer (71) located on the anode (70) and a cathode (72) located on the organic emitting layer (71); the connecting electrode (80) contacts the TFT (90) via the contact hole (81) penetrating the flat layer (60) and the passivation layer (50); the anode (70) is electrically connected to the TFT (90) via the connecting electrode (80); the short circuit between the cathode and anode of the OLED display substrate can be prevented for avoiding the current concentration and ensuring the normal illumination of the OLED.

Abstract: A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.