Abstract: A method of manufacturing a light scattering layer and an organic light-emitting diode are provided. The manufacturing method includes: depositing a material having a low refractive index value in hole structures of a mask on a base; removing the mask, and forming a plurality of raised structures on the base; depositing a material having a high refractive index value between the raised structures to form a planarization layer, thereby manufacturing a light scattering layer constituted by the raised structures and the planarization layer on the base. The manufacturing method has the advantages of being simple to prepare, low-cost, etc.

Abstract: An organic light emitting display device includes an overcoating layer on a substrate; a first electrode on the overcoating layer; a bank layer on the overcoating layer and the first electrode, the bank layer including an opening through which the first electrode is exposed; a pattern layer having an island shape on the exposed portion of the first electrode; an organic emission layer on the first electrode and the pattern layer; and a second electrode on the organic emission layer.

Abstract: A display device includes a stretchable display panel including a first display area and a second display area, the second display area extending from the first display area in a horizontal direction substantially parallel to the first display area, and a frame including a first coupling part and a second coupling part spaced apart from the first coupling part in the horizontal direction, the second coupling part being moveable in a vertical direction normal to the horizontal direction, wherein the first and second display areas are respectively coupled to the first and second coupling parts, and the second display area is elongated in the vertical direction when the second coupling part moves in the vertical direction.

Abstract: The present disclosure relates to perylene-based molecules and their use in photoelectric conversion layer(s) and/or an organic or hybrid image sensor. The present disclosure also relates to absorption layer(s) and photoelectric conversion layer(s) comprising a molecule according to the present disclosure. The present disclosure also relates to a device, comprising a photoelectric conversion layer comprising at least one perylene-based molecule. Moreover, the present disclosure relates to an organic image sensor or a hybrid Silicon-organic image sensor comprising photoelectric conversion layer(s) according to the present disclosure.

Abstract: A method for compensating non-linearities of a read signal generated by a variable-capacitance inertial sensor including a first fixed electrode and a second fixed electrode and a mobile electrode, which is spatially arranged between the first and second fixed electrodes and is capacitively coupled to the first and second fixed electrodes, said method comprising the steps of: acquiring the read signal; identifying a first linear component and at least one first nonlinear component of the read signal; a generating a compensated output signal by subtracting the first nonlinear component from the read signal.

Abstract: The present invention provides a Group III nitride semiconductor light-emitting device in which electrons and holes are suppressed from being captured by threading dislocation, and a production method therefor. The light-emitting device comprises an n-type contact layer, an n-side electrostatic breakdown preventing layer, an n-side superlattice layer, a light-emitting layer, a p-type cladding layer, a p-type contact layer, a transparent electrode, an n-electrode, and a p-electrode. The light-emitting device has a plurality of pits extending from the n-type semiconductor layer to the p-type semiconductor layer. The n-side electrostatic breakdown preventing layer has an n-type AlGaN layer. The n-type AlGaN layer includes starting points of the pits.

Abstract: A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.

Abstract: A display screen and a portable device are disclosed. The display screen includes a display region and a non-display region surrounding the display region, the display region includes at least one transparent antenna structure, the antenna structure includes an antenna and a capacitor which are located in a same layer, and the capacitor is electrically connected to the antenna. The portable device includes the display screen. The display screen and the portable device simplify the manufacturing process and also reduce the manufacturing difficulty.

Abstract: In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

Abstract: A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process.

Abstract: The invention provides a manufacturing method for LTPS TFT substrate. After forming N+ areas on both sides of polysilicon layer, the first gate insulating layer, first gate, second gate insulating layer, and second gate are sequentially formed on polysilicon layer, and the second gate is wider than first gate to produce a low electric field region in the polysilicon layer to reduce leakage current; alternatively, forming first gate and first gate insulating layer, forming polysilicon layer and N+ areas on both sides of polysilicon layer, forming second gate insulating layer and second gate on polysilicon layer, the second gate insulating layer is thicker than first gate insulating layer and the second gate is wider than first gate, so that the second gate insulating layer sandwiched by the second gate beyond first gate and polysilicon layer is thicker and produces a smaller electric field, which simplifies process and reduce cost.

Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.

Abstract: A plotter device measures movement distance of a moving body along with other device belonging to the same network, in which only of the devices belonging to the same network functions as a master, and a device other than the master functions as a slave. This plotter device includes a measurement component, a communication component, and a calculator. The measurement component adds the movement distance while the plotter device is functioning as the master to the master movement distance of the plotter device, and does not add the movement distance while the plotter device is functioning as the slave to the master movement distance of the plotter device.

Abstract: An organic light emitting display device includes a plurality of pixels defined on a substrate. Each of the plurality of pixels has a plurality of sub-pixels, and each of the plurality of sub-pixels has a light emitting area and a driving area. Widths in a first direction of the driving areas of the plurality of sub-pixels are identical to each other. A size of a light emitting area of a first sub-pixel of the plurality of sub-pixels is greater than a size of a light emitting area of a second sub-pixel of the plurality of sub-pixels.

Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.

Abstract: The present invention relates to the field of electronic devices, such as organic electronics, wherein said device includes a substrate and a multitude of layers, wherein at least one of said layers is a buffer layer, wherein said buffer layer includes metal oxide nanoparticles coated with dispersant as described in the specification. The invention further provides for electronic device component and materials suitable for manufacturing such electronic devices, to specific manufacturing methods and to specific uses.

Abstract: A manufacturing method of an organic thin film transistor includes: forming source and drain electrodes on a substrate; irradiating a photosensitive outer surface with a first charge of a photosensitive roller by laser to pattern the photosensitive outer surface and forming a channel pattern area without charge; spraying an atomized organic material solution with a third charge having same polarity as the first charge onto the channel pattern area to make the organic material solution be absorbed onto the channel pattern area and thereby form a channel region layer; attaching a fourth charge having an opposite polarity to the third charge onto a surface of the substrate disposed with the source and drain electrodes; and transferring a channel pattern in the channel region layer onto the substrate and connected with the source and drain electrodes and thereby forming a channel region. A manufacturing apparatus also is provided.

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Abstract: A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal transistors, the second structure overlaying the first single crystal transistors, where at least one of the second single crystal transistors is at least partially self-aligned to at least one of the first single crystal transistors; and at least one thermal conducting path from at least one of the first single crystal transistors and second single crystal transistors to an external surface of the device.

Abstract: A Schottky barrier diode is provided, which includes a semiconductor substrate, a first well region, an isolation region, a silicide layer and a silicon oxide-containing layer. The first well region of a first conductivity type is in the semiconductor substrate. The isolation region is in the first well region. The silicide layer is laterally adjacent to the isolation region, and over and in contact with the first well region. The silicon oxide-containing layer is over and in contact with the isolation region.