Abstract: An output circuit includes a first, second and third field effect transistors each having a channel of a first conductivity type. The first field effect transistor includes a gate connected to a first node, a first electrode connected to a first power supply and a second electrode connected to a second node. The second field effect transistor includes a gate connected to a third node, a first electrode connected to the second node, a second electrode connected to a fourth node and a substrate connected to a fifth node. The third field effect transistor includes a gate connected to a sixth node, a first electrode connected to the third node, a second electrode connected to the fourth node and a substrate connected to the fifth node. The output circuit further includes an inverter and a fourth field effect transistor having a channel of a second conductivity type which is opposite the first conductivity type.

Abstract: An output circuit for a high-breakdown-voltage power IC is provided. The output circuit includes a level-shift circuit on constant-current type including an output terminal connected to the gate of a p-channel MOSFET with a high breakdown voltage; a totem-pole circuit including an n-channel MOSFET with a high breakdown voltage on the high potential side of the totem-pole circuit, the gate of which is connected to the drain of the MOSFET via a high resistance; an n-channel MOSFET with a high breakdown voltage on the low potential side of the totem-pole circuit, and one single power supply having a plurality of terminals, the voltages thereof are different, used for a low-voltage power supply for driving the level-shift circuit and a high-voltage power supply for driving the totem-pole circuit.

Abstract: A power circuit for an integrated circuit chip having a plurality of operation frequency modes, the power circuit varying a resonance point defined by a parasitic resistance, inductance and capacitance existing in a power supplying line, in accordance with an operation frequency to thereby prevent the operation frequency from being in accord with a resonance frequency. For instance, when the operation frequency is relatively high, the power circuit lowers the resonance point, and when the operation frequency is relatively low, the power circuit raises the resonance point. The power circuit may further include an encoder receiving an operation frequency mode signal, and emitting an output signal indicative of an operation frequency. The power circuit provides a power ensuring stable operation of an external circuit in a plurality of operation frequency modes.

Abstract: An ignition system has several charging circuits connected to a common input circuit and controlled by a common triggering unit to fire respective igniters. The input circuit has a voltage source connected across a first capacitor, which provides the output terminals of the source. Each charging circuit has a second capacitor connected in series with one end of an inductance. A tapping of the inductance is connected to an input of the charging circuit via a diode and a thyristor, controlled by the triggering unit. The output of the charging circuit is provided by one electrode of the second capacitor and the opposite end of the inductance.

Abstract: The present invention discloses an output stage for a charge pump, mainly formed by transistors, for example, MOS-type transistors. This output stage includes capacitive elements intended to compensate charge/discharge phenomena of parasitic capacitances intrinsic to the transistors. A charge pump including such a stage may thus produce a low-value nominal current and enables to completely integrate a phase-locked loop demodulator.

Abstract: A voltage multiplier circuit or charge pump circuit for CMOS integrated circuits having high power efficiency, high current drive and efficient area utilization. An embodiment comprises two mirrored sections driven by control signals (PH00, PH01, PH0.sub.-- P; PH10, PH11, PH1.sub.-- P) generated by a logic circuitry which receives, as input signals, an enable signal (en) and a clock signal (clk), wherein each mirrored section includes N stages and each stage comprises a capacitor (C00, C01, C02; C10, C11, C12) having a lower terminal and an upper terminal, the lower terminal is connected to a first switch (INV0, NCH00, NCH01; INV1, NCH10, NCH11) that, in closed condition, couples the lower terminal of the capacitor to ground (GND), said lower terminal of the capacitor being additionally connected to a second switch (INV0, PCH00, PCH01; INV1, PCH10, PCH11) that, in closed condition, couples the lower terminal of the capacitor to the supply voltage (Vpp).

Abstract: The present invention provides a novel clock frequency divider that accepts an input clock having an input clock frequency and provides an output clock with an effective clock frequency of one of 1/N, 2/N, . . . , (N-1)/N, N/N times the input clock frequency, where N is an integer. The clock frequency divider of the present invention divides the input clock frequency asymmetrically by filtering out one or more of each N pulses on the input clock, as dictated by select signals. For example, in a clock frequency divider having N=8, a first clock output signal filters out one of each eight pulses, retaining seven pulses. Therefore, the effective frequency of the output clock signal is (N-1)/N, or 7/8, times the frequency of input clock signal. Similarly, a second output clock signal retains six of every eight pulses, a third retains five, and so forth.

Abstract: The present invention provides an input receiver that slows the signal fluctuation by limiting the amount of electrical currents flowing through the input receiver. The limiting of electrical current flowing through the input receiver slows the input signal of the receiver which in effect filters out some level of glitches of an input signal. In one embodiment, the input receiver is constructed and implemented in a structure similar to a differential amplifier for a single interface. In another embodiment, the input receiver is constructed and implemented in a modified differential amplifier for a single interface. In a further embodiment, the input receiver is constructed and implemented in a modified differential amplifier for multiple interfaces.

Abstract: The present invention provides improved output buffers for use on IC Chips. These output buffers incorporate a compensation circuit for compensating the performance characteristics of transistors included in the output buffers. The compensation circuit determines whether the output buffer is operating at a desired slew-rate. In response to this determination, the compensation circuit supplies a compensation voltage or voltages. The compensation voltages control a variable quantity of power delivered by a voltage controlled power source (VCPS). By increasing or reducing this power, the slew-rate of the output buffers are respectively increased or reduced. The compensation voltages maintain this slew-rate within narrow tolerances. This allows the improved output buffers of the present invention to meet very narrow input tolerances of circuitry coupled to receive signals from the IC Chip.

Abstract: A voltage reference generator (200) generates a temperature compensated voltage at an output (202). The voltage reference generator includes a first transistor (204) and a second transistor (206) series connected between a supply voltage and the output. The first transistor and the second transistor establishing the temperature compensated voltage in response to a bias current (I.sub.BIAS) and a first bias voltage and a second bias voltage. The voltage reference generator further includes a current source (208) coupled to the first transistor and the second transistor to establish the bias current in the first transistor and the second transistor. The current source produces the first bias voltage and the second bias voltage.

Abstract: A bus driver circuit for high speed data transmission includes a plurality of delay blocks connected in series one to another which varies a rise and fall time of an input signal in order to shape an output waveform. Each block includes one or more delay elements for providing a predetermined delay period. A selector input is provided for each delay block such that one or more of the predetermined delay periods can be selected. Hence, the rise and fall time of the input signal can be varied depending upon which block or combination of blocks have been selected to shape the resultant waveform. An output circuit is also included which superimposes the input signal on the resultant output waveform.

Abstract: A temperature dependent constant-current generating circuit includes a reference voltage generating circuit for generating a stable reference voltage against the power supply voltage and a temperature change, a stabilized voltage generating circuit for generating a stabilized voltage based on the reference voltage, a voltage divider for dividing the reference voltage, a common-emitter amplifier for amplifying an output voltage from the voltage divider, a current mirror circuit for outputting a current in a direction opposite to an output current from the amplifier, a current-to-voltage conversion resistor connected between the output terminal of the stabilized voltage generating circuit and the output terminal of the current mirror circuit, a buffer amplifier for receiving a voltage generated at the current input terminal of the resistor, and a current feedback output-stage amplifier driven by an output from the buffer amplifier.

Abstract: An IC includes a clamp transistor for limiting the voltage at a circuit node and a current amplifier coupled across the input and output terminals of the clamp transistor. In one embodiment the current amplifier comprises a current mirror. In a differential line driver, the direction of current through a load is controlled by means of pair of dual-function transistors which also serve to provide current gain in separate current mirrors.

Abstract: A high voltage generation circuit includes an inductor, a PN diode, a capacitor and a transistor. A high voltage sampling/division circuit, a control register, a voltage comparator, a counter, a pulse generation circuit and a ring oscillator in the high voltage generation circuit detect whether voltage generated through the capacitor is a desired high voltage or not and generates a pulse signal which controls ON/OFF of the transistor. Accordingly, a path of current flowing into the capacitor is changed and the generated voltage is digitally adjusted.

Abstract: A semiconductor memory device for providing a burst mode control signal. The semiconductor memory device includes a first logic circuit for generating a driving signal in response to a first logic level of an externally input write and read control signal and an externally input chip enable signal, a plurality of transition registers for respectively changing the driving signal in synchronization with a first edge of a clock signal to generate changed driving signals, and a second logic circuit for generating the burst mode control signal generated by the logic combination of the changed driving signals in response to a read latency control signal.

Abstract: In a substrate potential control circuit, first and second substrate potential detection circuits have different intersected characteristics of Vcc versus V.sub.SUB detection level and produce, in response to a substrate potential V.sub.SUB, first and second substrate potential detection signals SUBUP1 and SUBUP2, respectively. A composition circuit composes the first and the second substrate potential detection signals SUBUP1 and SUBUP2 to produce a composite substrate potential detection signal SUBUP. Responsive to the composite substrate potential detection signal SUBUP, a back bias generation circuit generates a back bias signal BBG. Responsive to the back bias signal BBG, a pumping circuit makes the substrate potential V.sub.SUB by pumping.

Abstract: An apparatus for protecting an integrated circuit against damage from electrostatic discharges (ESD) includes a single ESD bus that is connected to multiple input pads through a respective diode. The ESD bus is isolated from the positive power supply bus V.sub.DD. The ESD bus is coupled to the negative power supply bus V.sub.SS by a FET-triggered SCR circuit. ESD charge on an input pad forward biases the respective diode and charges the ESD bus. When the voltage of the ESD bus reaches a predetermined threshold voltage, the FET breaks down, and triggers the SCR circuit to shunt the charge on the ESD bus to V.sub.SS. The threshold voltage is selected such that, in normal operation, voltages higher than V.sub.DD may be applied to the input pad without input leakage current.

Abstract: A scalable level shifter which performs at high-speeds and optimizes power consumption. The scalable level shifter receives an input signal and converts the input signal having a scalable voltage level to an output signal having a predetermined voltage level. The scalable level shifter includes a self-resetting circuit connected to an internal power supply for interrupting an internal current path responsive to output signal voltage variations corresponding to voltage transitions of the input signal.

Abstract: A power consumption control circuit for CMOS circuit for achieving a constant signal propagation delay time in the CMOS circuit by maintaining the same power consumption all the time. A leading edge heater and a trailing edge heater are provided in close proximity to the CMOS circuit. During a time period for a leading edge of an input pulse propagates through the CMOS circuit, the leading edge heater is turned off. During a time period for a trailing edge of the input pulse propagates through the CMOS circuit, the trailing edge heater is turned off. As result, an overall current flowing in the CMOS circuit, leading and trailing edge heaters is unchanged regardless of the repetition rate of the input pulse provided to the CMOS circuit.

Abstract: A voltage multiplier has two mirrored sections which are clocked by nonoverlapping phases. Each section of the voltage multiplier has N stages: each stage is made of a capacitor and MOS transistors operating as switches. During a charging phase, the N capacitors are insulated from each other and the terminals of each capacitor are connected one to voltage Vpp and the other to ground GND by means of PMOS transistors. During the discharge phase, the N capacitors are connected in series, with the bottom plate of the first stage capacitor coupled to ground voltage GND and the top plate of the last-but-one stage capacitor coupled to the output through a PMOS transistor. The gate voltage of this PMOS transistor is furnished by the last stage, in the upper portion of the circuit, in order to drive the transistor into a fully on condition.