Abstract: A current reference circuit is capable of operation at a very low supply voltage, such as 1 volt. The current reference circuit is composed of a current mirror circuit, serving as an inverse PTAT (i.e., inversely proportional to absolute temperature) subcircuit, and a PTAT subcircuit for driving the current mirror circuit. The current mirror circuit and the PTAT subcircuit are mutually biased to each other. First and second constant currents produced by the PTAT subcircuit are supplied to the current mirror circuit as its reference and mirror currents, thereby cancelling the temperature coefficients of the first and second constant currents.

Abstract: A slew rate control circuit to control output slew rate according to a programmable reference signal. A slew rate control circuit limits the slew rate of a plurality output buffers according to a signal received from a programmable slew rate control reference.

Abstract: An improved CMOS current source circuit capable of constantly generating a certain reference voltage irrespective of an analog supplying voltage, a substrate temperature, and a temperature variation, which includes a start unit for driving the CMOS current source circuit in accordance with a start signal; a bias current generating unit driven by the start unit for generating a bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation; a current input unit for inputting a bias current; and a current compensation unit for receiving a bias current through the current input unit and for compensating the bias current in accordance with an analog voltage, a substrate voltage, and a temperature variation and for generating a reference current.

Abstract: A CMOS circuit (10), which is integrated in a semiconductor substrate, comprises a principal circuit part (12), which includes the major part of the circuit components in a well isolated from the substrate by a substrate diode. The CMOS circuit furthermore comprises a power output stage (16) driving an inductive load (26, 28). A sensor (18) is connected with one output (22, 24) of the power output stage (16) and on detection of a voltage biasing the substrate diode (30, 32) in the conducting direction produces a switching signal at the output. On occurrence of the switching signal produced by the sensor (18) a controllable switch (20) disconnects the supply voltage from the principal circuit part (12). In its own separate well (46) a status memory (14) is formed on the substrate adjacent to the principal circuit part (12), such status memory (14) comprising memory elements for storage of status data of the principal circuit part (12) on disconnection of the supply voltage.

Abstract: A bias circuit for obtaining accurate on-chip time constants and resistances. The bias circuit includes a constant-g.sub.m bias circuit and feedback loop circuit. The constant-g.sub.m bias circuit has a mos transistor device and a variable resistor device which are arranged so that the trandsconductance of the transistor device is dependent upon the resistance of the resistor device. The constant-g.sub.m bias circuit generates a bias output signal that is a function of the trandsconductance of the transistor device. The feedback loop circuit includes signal generation means responsive to the bias output signal for generating a signal that is a function of the bias signal. The loop circuit further includes a comparison means for comparing the generated signal to a known external frequency reference, and an output that is operatively connected to the variable resistor device for adjusting the value of the variable resistor device until the generated signal matches the external reference signal.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: An insulated-gate field effect transistor comprising a channel forming region, source/drain regions, a gate region, a bias supplying means, and a capacitive element, wherein a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the channel forming region through the bias supplying means, and a signal having approximately the same phase as a phase of a signal supplied to the gate region is supplied to the channel forming region through the capacitive element.

Abstract: For providing a voltage booster circuit wherein the output voltage is boosted up with a sufficient ability, and smoothly and easily controlled as well to maintain a desired voltage level with little fluctuation, the voltage booster circuit of the invention comprises a plurarity of pumping circuits (1--1 to 1-n), each thereof connected in parallel between a power supply (Vcc) and an output terminal (VPUMP) for supplying a higher voltage than the power supply, driven by a pair of complementary pumping clocks; means for generating pump activating signals determining a number to be activated of said plurality of pumping circuits according to potential of the output terminal; and switching means (6-1 to 6-n) for supplying the pair of complementary pumping clocks to each of the number to be activated of the plurality of pumping circuits controlled with said pump activating signals.

Abstract: A power supply switching circuit comprises first and second PMOSFETs connected in series between a writing high voltage and an output terminal in the named order, and third and fourth PMOSFETs connected in series between a reading voltage and the output terminal in the named order. A substrate potential of the first PMOSFET is connected to the writing high voltage, and a substrate potential of the third PMOSFET is connected to the reading voltage. A substrate potential of the second and fourth PMOSFETs are connected in common to a substrate potential control circuit which is configured to selectively supply either the writing high voltage or the reading voltage to the common connected sub.about.t rate potential of the second and fourth PMOSFETs.

Abstract: A power supply for supplying a power supply potential to a first stage input buffer circuit of a semiconductor device is changed according to the types of first stage input circuits. For example, an external power supply potential is supplied without change in a value from an external power supply to a first stage input buffer circuit to which a signal which activates a circuit provided in the subsequent stage only by transition from an "H" level to an "L" level such as an RAS signal. Thus, reduction in power consumption can be achieved. A stable internal power supply potential obtained by down-converting an external power supply potential is supplied from an internal power supply to a first stage input circuit to which a signal which activates a circuit provided in the subsequent stage by any one of transitions from an "L" level to an "H" level and from an "H" level to an "L" level. Thus, output information can be stabilized.

Abstract: An LSIC includes a clock distributor circuit capable of decreasing the power consumption and suppressing the deviation of the power source potential and the transient current. The circuit includes a plurality of functional blocks including CPU. The CPU conducts a data accessing operation via address and data buses to peripheral blocks. There is also provided a clock supply unit to supply clock signals in which at least one of the clock signals has a phase different from those of the remaining clock signals and the clock signals do not accomplish the setting operation at the same time.

Abstract: A CMOS voltage generator for providing a reference voltage VDD2 that will track the low level power supply voltage VDD (approximately 3.0V-3.6V) as long as the power supply is present. When VDD is not present (defined as at "hot pluggable" condition), the voltage generator is configured to maintain a "protection" output voltage less than the relatively high voltage (approximately 5V) that may appear along a circuit signal bus. In particular, the circuit includes at least a pair of diode-connected N-channel devices disposed between the signal bus line and the output voltage terminal to provide the necessary protection.

Abstract: A gm-C circuit includes a two-stage common mode control loop to limit the common mode voltage during circuit operation. To prevent latch-up in a cross-coupled differential gm-C type filter, the common mode control loop includes a circuit which provides extra current capability to the common-mode control loop without increasing the quiescent, current. This is accomplished by a current boost technique that provides large amounts of current when needed, while running in a low current mode under normal circumstances.

Abstract: A circuit arrangement (16) for producing a D.C. current, includes a feedback loop for producing a reference current from an output terminal (27) with a negative temperature coefficient. The feedback loop includes a current-source stage (17, 18) which feeds a current mirror stage (19, 20, 21) in response to a measuring current supplied from a current bank (24, 25, 28, 29), which also produces the output reference current. The output of the current mirror stage (19, 20, 21) drives a working impedance formed by the main current path of a transistor 22, across which a control voltage is developed which is applied to a control input (23) of the current bank (24, 25, 28, 29). The circuit arrangement is advantageously combined with a reference current source (1) arranged as a bandgap circuit for producing a reference current on an output terminal (2) with a positive temperature coefficient, by enabling the user to select a current reference with either a positive or negative temperature coefficient.

Abstract: A capacitor (C) and a Zener diode (ZD2) are connected in parallel to a high-voltage side drive circuit (2). when a Zener voltage (VZD2) is set 5V, a voltage which is charged up in the capacitor (C) is determined by the Zener voltage (VZD2). Hence, it is only necessarv to set a voltage (VCC) in a loxv-voltage d.c. power source (4) at a value which is higher than (VZD2+VD+VCE), where VD is a forward-direction voltage to a diode (Di) and VCE is an ON-voltage to a low-voltage side switching device (Q1). Since a variation in a charging voltage which is supplied to a high-voltage side drive circuit is suppressed, it is possible to drive a switching device with 5V.

Abstract: A bus driver circuit having slew rate control. According to one embodiment, the bus driver circuit includes the following elements: a first circuit having an input configured to receive a data signal and an output operative to output a drive signal in response to the data signal; a second circuit coupled in parallel with the first circuit and operative to receive a slew rate control signal; and a slew rate indicator circuit coupled to the second circuit. The slew rate indicator circuit determines the state of the slew rate control signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signal is asserted, the second circuit is enabled to affect the slew rate of the drive signal. For one embodiment, the slew rate indicator includes a pulse generator circuit and a clocked comparator circuit.

Abstract: An integrated circuit selectively operable in either a first mode (consuming low power) or a second mode (consuming relatively high power). The circuit includes MOS transistors and a supply voltage circuit for at least one of the transistors. In both modes, the supply voltage circuit holds the body of each transistor at a fixed voltage (e.g., a voltage V.sub.CC in a range from 5 to 5.5 volts, where each transistor is a PMOS device). In the second mode the supply voltage circuit supplies this fixed voltage to the source of each transistor, but in the first mode it supplies a voltage equal to or slightly offset from the fixed voltage to the source of each transistor. In some embodiments, the supply voltage circuit (in the first mode, after an initial transient state) supplies a first voltage to a well shared by a plurality of PMOS transistors, and a second voltage to the source of each PMOS device.

Abstract: A semiconductor device (e.g., a zero-delay buffer) is provided which is capable of reducing current or power consumption without the use of a dedicated pin. The device may include a frequency detector that receives a detector input signal corresponding to or derived from a device input signal. The device input signal performs a first function during normal operation of the device. The detector determines whether the frequency of the detector input signal is less than a predetermined minimum, and if so, generates a power down signal configured to direct the device to reduce current or power consumption in at least one of its component circuits. The frequency detector may include a "one-shot" circuit responsive to the detector input signal for generating a frequency indicator signal, and a "power down" signal output circuit responsive to the frequency indicator signal for generating the power down signal.

Abstract: A capacitor is connected between the gate of a transistor that is an object of threshold voltage compensation and an input terminal. A switching device is connected between a current source connected to one terminal of the transistor and the gate of the transistor. A second switching device is connected between the input terminal and a terminal to which a reference voltage is applied. The switching device is turned ON so that the transistor is diode-connected. The switching device is turned ON, thus applying the reference voltage to the input terminal. A reference voltage is applied to a current inflow terminal connected to another terminal of the transistor. After charge dependent on the threshold voltage of the transistor is accumulated in the capacitor, the switching device is turned OFF. With this control, a difference of a threshold voltage from another deriving from the fine structure of transistors as well as a difference in threshold voltage between adjoining transistors can be compensated for.

Abstract: The present invention discloses an integrated constant bias voltage generator using only active devise to simulate a high impedance node, as seen from a capacitively coupled input signal. A reference current source an MOS device are coupled in series between Vcc and ground with the drain electrode of the MOS device being the constant bias voltage output. An input signal capacitively coupled to said drain electrode introduces an error current monitored by a current monitoring means. A feedback means responsive to the current monitoring means modulates the control input of the MOS device to select a IDS vs. VDS characteristic curve which will maintain the VDS voltage constant for any given IDS current, including the error current. The feedback means also compensates for voltage fluctuations in Vcc.