Abstract: A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS transistor means connected between a stage input terminal and a stage output terminal allowing current to flow only from said stage input terminal to said stage output terminal, and a first capacitor with one plate connected to said stage output terminal and another plate driven by a respective first digital signal periodically switching between ground and said voltage supply.

Abstract: An apparatus and method for deriving a signal from the AC line and conveying it to processing circuitry employs two wires each of which is non-conductively attached and capacitively coupled to a respective one of a two-wire AC power line. Each of the capacitive pick-offs is coupled to a respective input of a differential amplifier for amplification. Advantageously, because the output signal is a replica of the AC power line signal, the detection threshold can be set at or near zero volts. This makes the detection point insensitive to the amplitude variations of the AC power line. In one embodiment, an output signal is developed at a single ended output of the differential amplifier, and applied to a low pass filter to remove undesired higher frequencies. A further amplifier provides greater amplification of the filtered representation of the AC power line signal, and includes an amplitude limiting circuit to accommodate the wide range of AC line voltages which may be applied to the instrument.

Abstract: A voltage generating circuit for a semiconductor memory cell using a complementary MOS (CMOS) circuit uses an external clock signal on behalf of an internal oscillator clock signal as an input signal for driving an electric charge pumping portion, and performs a pumping operation which actively corresponds to the external input environment.

Abstract: An integrated sample-and-hold S/H circuit includes a subthreshold conduction current compensation circuit for reducing undesired effects of subthreshold conduction current in a first field-effect transistor (FET) during the holding time. More particularly, the S/H circuit may include a substrate, a sampling capacitor formed on the substrate, and the first FET. The first FET has a first conduction terminal for receiving the input signal, a second conduction terminal connected to the sampling capacitor, and a control terminal. The control terminal is responsive to control signals for connecting the input signal to the sampling capacitor during a sampling time and for disconnecting the input signal from the sampling capacitor during a holding time. The first FET preferably further includes a body which unfortunately creates a parasitic diode connected to the sampling capacitor.

Abstract: An active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines.

Abstract: A current mirror circuit includes an input transistor and an output transistor. A first bipolar transistor has a collector terminal connected to a predetermined reference portion of a current supply path of a power source and an emitter terminal connected to a collector terminal of the output transistor for absorbing an electrical potential difference between the reference portion and the collector terminal of the output transistor. A second bipolar transistor has a base terminal connected to the emitter terminal of the first bipolar transistor and a collector terminal connected to a base terminal of the first bipolar transistor for fixing an electrical potential of the collector terminal of the output transistor to a base-emitter voltage of the second bipolar transistor.

Abstract: In response to complementary clock signals provided from a driver, a charge pump operates to provide an output voltage which is a down-converted negative voltage. The voltage between this output voltage and a predetermined positive reference voltage is capacitance-divided by capacitors. The capacitance-divided positive voltage is applied to a comparator, whereby a reference voltage is compared with the above positive voltage. An output signal of the comparator is applied to the driver. In response, the driver controls the operation of the charge pump, whereby the output voltage is clamped at a predetermined voltage level for output.

Abstract: A low-skew single-ended to differential signal converter includes a conventional single-ended to differential converter that drives a pair of output driver circuits. Each driver circuit is formed from a pair of transfer gates that receive a supply voltage or a reference voltage, respectively. The transfer gates transfer only a portion of the supply or reference voltage in response to the inverted signal from the conventional converter. The portion of the transferred voltage is insufficient to trigger output members in the output drivers and the output voltages from the drivers do not transition in response to the noninverted signal. The inverted signal causes the outputs of the transfer gates to transition fully, triggering the respective output inverters. Because the inverted signal causes transitions of both of the output signals, skew of the output signals is reduced relative to skew of the inverted and noninverted signals.

Abstract: Disclosed is a biasing circuit for bringing a power FET to a substantial full enhancement. The biasing circuit includes: (a) a rail power voltage that is coupled to a drain terminal of the power field effect transistor; (b) a load being coupled between an other potential and a source terminal of the power field effect transistor; and (c) a micromachined DC/DC converter that is coupled between a gate terminal of the power field effect transistor and the rail power voltage. The micromachined DC/DC converter is configured to produce an enhanced voltage that is greater than the rail power voltage to the gate terminal of the power field effect transistor to achieve a substantial enhancement of the power field effect transistor.

Abstract: A control circuit for Hall-effect switching device is provided. The control circuit can be used in a Hall-effect switching device to control the output of the Hall-effect switching device in response to Hall effect. The control circuit comprises a current source and two pairs of symmetrically arranged bipolar junction transistors (BJT). The particular arrangement of the BJTs allow the Hall-effect sensitivity by the Hall-effect switching device to be enhanced. The Hall-effect sensitivity can be adjusted by varying the current source in the control circuit. Moreover, the control circuit is designed with a double-output feature that allows the Hall-effect switching device to be realizable with a fewer number of transistors, allowing the Hall-effect switching device to operate with a lower working current and a lower starting voltage as compared to the prior art, thus considerably reducing power consumption.

Abstract: A regulator circuit (10, 50) for connection to a high voltage generator (16, 52). The regulator circuit may be coupled to the generator in either a series or a shunt configuration. In the shunt configuration, the regulator circuit (10) varies the amount of current through a shunt resistor (R1) to change the output voltage provided to a load. The amount of current that is shunted by the regulator circuit is controlled by a feedback circuit consisting of a voltage divider (20) and an error amplifier (22). In the series configuration, the voltage across the regulator circuit (50) is added to the output from the high voltage generator. The current conducted through the regulator circuit therefore varies the summed output provided to the load.

Abstract: A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal.

Abstract: A low voltage charge pump system with a large output voltage range is described. The charge pump system comprises eight charge pump stages, an output stage, and a four phase clock generator. The clock generator generates two sets of four phase shifted signals. The first set of four clock signals are coupled to the first four charge pump stages and have a logic high level of VCC. The second set of clock signals are coupled to the second four charge pump stages and have a logic high level of 2 VCC. Due to the body effect, the negative voltages at the charge pump output stages increases the threshold voltage of a pass transistor which couples the input and output in each charge pump. The larger high voltage level of the second set of clock signals enables the signals to overcome the body effect increased threshold voltages of the pass transistors. The pass transistors are then used to couple negative charge to the next charge pump stage, and positive charge to the preceding charge pump stage.

Abstract: First and second spaced-apart planar circuit ground conductors are formed on a base substrate. Multiple stages of an amplifier each have a field effect transistor (FET) flip mounted onto the substrate. A signal-return line couples the sources of the FETs together and functions as a radio frequency (RF) grounds for the amplifier. Direct-current-blocking coplanar couplers couple the amplifier input and output to external circuits. A single voltage supply applies a bias voltage to the drains of the FETs. A source resistance device couples each source terminal to circuit ground. The source resistance devices may be formed of two series-connected resistors. The gate of each FET is coupled to one of the circuit ground conductors through one of the source resistors. The other source resistor thereby provides a gate-to-source voltage for biasing the FET.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: A fault tolerant circuit arrangement includes: an input; an output; a first circuit element, a second circuit element, a third circuit element, and a fourth circuit element, provided in such a manner that the first and second circuit elements are connected in series between the input and the output to form a first series combination, and the third and fourth circuit elements are connected in series between the input and the output to form a second series combination, the first series combination being connected in parallel with the second series combination between the input and the output; and, a control element connected between an interconnection point of the first and second circuit elements and an interconnection point of the third and fourth circuit elements. The control element is switchable by a control signal between a conducting mode in which current flow is enabled between the interconnection points and a non-conducting mode in which current flow is prevented between the interconnection points.

Abstract: A voltage boosting power supply circuit of a memory integrated circuit and a method for controlling charge amount of a voltage boosting power supply. The voltage boosting power supply circuit includes first and second power suppliers, first and second fuses, a voltage boosting controller, a voltage boosting enabling unit, and a voltage booster. The first and second power suppliers supply power supply. Each of one ends of the first and second fuses is connected to the first and second power suppliers. The voltage boosting controller generates first and second control signals a voltage boosting controller for generating first and second control signals, responding to a voltage boosting control signal which is in a ground voltage state before signals generated from each of other ends of the first and second fuses and the power supply become stable, and becomes logic high when the power supply becomes stable.

Abstract: A circuit to provide a burn-in reference voltage that is stable with respect to temperature and manufacture. The burn-in reference voltage circuit produces a burn-in reference voltage related to an external reference voltage. The circuit includes a feedback circuit to produce a feedback voltage that tends to the internal reference voltage in response to a deviation of the feedback voltage, from the internal voltage. The feedback voltage is mirrored to produce a mirrored voltage having the same magnitude as the feedback voltage but measured with respect to the external reference voltage.

Abstract: In integrated circuits, to modify the operation of the charge pumps or voltage step-up circuits, they are sent a variable frequency signal at the input with the aim of breaking the regularity of the pulse train that enters the charge pump. This limits the risks of entry into resonance and limits radiation at a given frequency. The variable frequency signal is typically produced by a logic circuit and by a main oscillator whose transmission of certain pulses is masked by the combined action of different masking signals. The duty cycle ratios of the masking signals are less than that of the signal from the main oscillator. Such duty cycle ratios are preferably produced following the passage of a signal to a lower frequency than that of the signal of the main oscillator in a circuit for the detection of high transitions.

Abstract: The present invention provides a reference voltage generating circuit for generating a stable reference voltage and having a long life time, and the reference voltage generating circuit for generating a reference voltage of a ferroelectric memory device having a plurality of bit line pairs, including: a first and second reference word line; a first dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of the switching transistors are coupled to the first reference word line and drains/sources of the switching transistors are coupled to a bit line of one of the bit line pairs; a second dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of the switching transistors are coupled to a second reference word line and drains/sources of the switching transistors are coupled to a bit bar line of one of the bit line pairs; and a reference plate line commonly coupled to the ferroelectric ca