Abstract: A data processing apparatus includes a data processor, and a data store for storing a plurality of identifiers identifying a cache way in which a corresponding value from a set associative cache is stored. The plurality of identifiers corresponding to a plurality of values stored in consecutive addresses such that a data store stores identifiers for values stored in a region of said memory. Included is a current pointer store for pointing to a most recently accessed storage location in said data store and circuitry to determine an offset of an address of said cache access request to an immediately preceding cache access request. Lookup circuitry determines if said pointer is pointing to an address within said region and said data processor identifies said cache way from said stored identifier pointed to by said current pointer if it has a valid indicator associated therewith.

Abstract: An extractor extracts a plurality of storage areas storing identical data strings therein from the storage areas of a lower storage layer. A layer storage controller associates the extracted storage areas with a single storage area of an upper storage layer.

Abstract: By taking advantage of parallel data processing and transmission techniques, the data access rate of a redundant array of independent disks (RAID) level 5 can be boosted significantly. A data distribution and aggregation unit is utilized to distribute a data stream into a plurality of data sub-streams based on the primitive data access block of storage devices as a processing unit of data writing, or to aggregate a plurality of data sub-streams to form a data stream based on the primitive data access block of storage devices as a processing unit of data reading. An exclusive OR operation unit capable of parallel data processing is introduced for performing data processing on the plurality of data sub-streams simultaneously. The data transmission of each data sub-stream is controlled individually by one of a plurality of transmission controllers.

Abstract: The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level page-walks with an out-of-order memory controller. In embodiments of the invention, the multi-level page-walk apparatus includes a demotion-based priority grant arbiter, a page-walk tracking queue, a page-walk completion queue, and a command packetizer.

Abstract: Methods (100), systems (300) and computer program products are disclosed for uninterrupted execution of an application program (110). The method (100) comprises: receiving a write operation call to a native file system from an application program (110) being executed on an operating system; and dynamically allocating (120, 122) free data blocks to the native file system from at least one other file system in a group of file systems until completion of execution of the application program (110) thereby completing the write operation call. The group of file systems is configured to allow sharing of free data blocks amongst the group of file systems.

Abstract: A system and method are disclosed for maintaining a plurality of data storages coherent with one another for redundancy purposes. The system includes a first data storage system and a second data storage system. The first data storage system is coupled to a first transaction processor for handling input and output transactions, and is coupled to a wide area network. The second data storage system is coupled to a second transaction processor for handling input and output transactions, and is coupled to the wide area network. The first transaction processor permits a first data write transaction to occur with respect to data within the first data storage system, and the second transaction processor permits a second data write transaction to occur with respect to data within the second data storage system.

Abstract: In a storage system, a technique for promptly reading the backup data stored in the child storage device in the remote site side in case of disaster for the master site is provided. In this system, a parent storage device having a primary volume (V1) and a secondary volume (V2) is arranged at a master site, and a child storage device having a backup volume to store data of V2 is arranged at a remote site, and remote backup of data of V1 is carried out. In the remote site side, management information of objective volume is stored in one of devices. When the data of the backup volume is read, for example in one child storage device, a process is carried out where the management information is read, and on the basis thereof, data of a plurality of backup volumes is collected and integrated as one volume.

Abstract: A computer-implemented method for determining whether to perform a computing operation that is optimized for a specific storage-device-technology type may comprise: 1) performing at least one proximate read operation by accessing a control location on a storage device and then accessing a test location on the storage device that is logically proximate to the control location, 2) performing at least one remote read operation by accessing a test location on the storage device that is logically remote from the control location, 3) determining, by comparing a length of time to access the proximate test location with a length of time to access the remote test location, a technology type of the storage device, and then 4) determining, based on the technology type of the storage device, whether to perform the computing operation. Corresponding systems and computer-readable media are also disclosed.

Abstract: In an apparatus for controlling the access operation by a plurality of data processing devices to a memory, each data processing device (10, 11, 12) is assigned a respective address region which indicates the part of the addresses of the memory (13) which the respective data processing device can access. A control device (21) blocks an access operation by a data processing device to the memory (13) if the access operation address is not located in the address region which is assigned to the respective data processing device (10, 11, 12).

Abstract: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

Abstract: An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.

Abstract: One embodiment of the invention is a method for evicting data from an intermediary cache that includes the steps of receiving a command from a client, determining that there is a cache miss relative to the intermediary cache, identifying one or more cache lines within the intermediary cache to store data associated with the command, determining whether any of data residing in the one or more cache lines includes raster operations data or normal data, and causing the data residing in the one or more cache lines to be evicted or stalling the command based, at least in part, on whether the data includes raster operations data or normal data. Advantageously, the method allows a series of cache eviction policies based on how cached data is categorized and the eviction classes of the data. Consequently, more optimized eviction decisions may be made, leading to fewer command stalls and improved performance.

Abstract: A method and terminal for demand paging at least one of code and data requiring a real-time response is provided. The method includes splitting and compressing at least one of code and data requiring a real-time response to a size of a paging buffer and storing the compressed at least one of code and data in a physical storage medium, if there is a request for demand paging for the at least one of code and data requiring the real-time response, classifying the at least one of code and data requiring the real-time response as an object of Random Access Memory (RAM) paging that pages from the physical storage medium to a paging buffer, and loading the classified at least one of code and data into the paging buffer.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.

Abstract: An exemplary storage network, storage controller, and methods of operation are disclosed. In one embodiment, a method of managing cache memory in a storage controller comprises receiving, at the storage controller, a cache hint generated by an application executing on a remote processor, wherein the cache hint identifies a memory block managed by the storage controller, and managing a cache memory operation for data associated with the memory block in response to the cache hint received by the storage controller.

Abstract: An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag.

Abstract: Embodiments of the present invention provide a system that selectively performs lookups for cache lines. During operation, the system by maintains a lower-level cache and a higher-level cache in accordance with a set of rules that dictate conditions under which cache lines are held in the lower-level cache and the higher-level cache. The system next performs a lookup for cache line A in the lower level cache. The system then discovers that the lookup for cache line A missed in the lower-level cache, but that cache line B is present in the lower-level cache. Next, in accordance with the set of rules, the system determines, without performing a lookup for cache line A in the higher-level cache, that cache line A is guaranteed not to be present and valid in the higher-level cache because cache line B is present in the lower-level cache.

Abstract: An apparatus and method of time keeping for a non-real-time OS is provided. The apparatus includes a processor and a Field Programmable Gate Array (FPGA). The processor requests performance of a Dual-Port Random Access Memory (DPRAM) read/write (R/W) operation in a DPRAM R/W time interval in a Time Division Multiple Access (TDMA) scheme using a system clock. Upon receipt of the DPRAM R/W operation performance request from the processor, the FPGA compares the operation performance request time with an access time table defining a DPRAM R/W time interval for each processor, generated in the TDMA scheme using the system clock. The FPGA performs the operation requested by the processor when the operation performance request has been made in the DPRAM R/W time interval of the processor.