Abstract: A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems.

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Abstract: A method to produce a reverse skip list data structure in a computer readable medium, comprising: inputting streamed data to packets created in a temporary memory so as to create a sequence of packets; upon completion of creation of a packet in the stream, transferring the completed packet from the temporary memory to persistent memory; providing each of a plurality of respective packets with a respective pointer that skips over at least one other packet in the packet sequence and that indicates a location in persistent memory of a different respective packet in the packet sequence that was transferred to persistent memory prior to such providing of the respective pointer.

Abstract: The present disclosure provides a method in a data storage system. The method includes defining a plurality of jobs for a command received from a host. Each of the plurality of jobs is associated with one or more of a plurality of data storage resources of the data storage system. The plurality of jobs have a defined order that is a function of addresses of data in the plurality of data storage resources. The method also includes issuing the plurality of jobs to the associated data storage resources and receiving information from the data storage resources for the plurality of jobs. The information is received by a controller of the data storage system for the jobs in an order that is different than the defined order. The method includes transmitting the received information to the host for the plurality of jobs in the defined order.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design can be provided. The design structure includes a symmetric multiprocessing (SMP) system. The system includes a plurality of nodes. Each of the nodes includes a node controller and a plurality of processors cross-coupled to one another. The system also includes at least one cache directory coupled to each node controller, and, invalid state transition logic coupled to each node controller. The invalid state transition logic includes program code enabled to identify an invalid state transition for a cache line in a local node, to evict a corresponding cache directory entry for the cache line, and to forward an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line.

Abstract: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring.

Abstract: A method and a computer readable medium having executable instructions are provided. The method and instructions when executed generates a first look-up key from a group of look-up key units stored in a data storage, generation of the first look up key being completed prior to the completion of a key generation processing cycle. A next look-up key unit from the group of look-up key units stored in the data storage may be skipped over when the next look up key corresponds to a second look-up key that has a key length equal to or smaller than a predetermined key length. A third look-up key unit may be selected from the group of look-up key units, the third look-up key unit associated with a third look-up key having a key length greater than a second predetermined key length, the second predetermined key length being greater than the first predetermined key length. The first look-up key and a portion of the third look-up key sequentially may be output during the same output processing cycle.

Abstract: A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism.

Abstract: In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

Abstract: Virtual machine optimization and/or storage reclamation solutions are disclosed that manage virtual machine sprawl and/or growing enterprise storage costs. For instance, certain solutions receive recommendations based on one or more rules, policies and/or user preferences that identify storage and/or alignment criteria for virtual machine disk (VMDK) partition(s). In certain examples, a resize tool that operates within a host operating system of a host server dynamically resizes and/or aligns one or more VMDK partitions of a powered-down virtual machine. For instance, the resize tool can be injected to the host server from a remote management server and can resize and/or align the VMDK partitions without requiring contents of the VMDK to be copied to another VMDK. By reallocating storage and/or aligning the VMDK partitions, embodiments of the invention can increase virtual machine performance and improve storage management.

Abstract: According to one embodiment of the invention, a processor comprises a memory, a plurality of core-cache clusters and a scalability agent unit that operates as an interface between an on-die interconnect and multiple core-cache clusters. The scalability agent operates in accordance with a protocol to ensure that the plurality of core-cache clusters appear as a single caching agent.

Abstract: A multiport semiconductor memory device and a multiprocessor system employing the same directly accesses a shared nonvolatile memory. The multiport semiconductor memory device includes a plurality of port units coupled with respective corresponding processors. A shared memory area is accessed by both the processors through the port units. A data path control unit controls a data path between the shared memory area and the port units and data transmission/reception is performed between the processors through the shared memory area. An access authority information storage unit is positioned outside of the memory cell array and stores information for an access authority of nonvolatile memory and provides the information to the processors. Accordingly, a direct access is performed by a processor indirectly connected to nonvolatile memory.

Abstract: A method for preventing subversion of address space layout randomization (ASLR) in a computing device is described. An unverified module attempting to load into an address space of memory of the computing device is intercepted. Attributes associated with the unverified module are analyzed. A determination is made, based on the analyzed attributes, whether a probability exists that the unverified module will be loaded into a number of address spaces that exceeds a threshold. The unverified module is prevented from loading into the address space if the probability exists that the unverified module will be loaded into a number of address spaces that exceeds the threshold.

Abstract: A memory control apparatus, a memory control method and an information processing system are disclosed. Fetch response data retrieved from a main storage unit is received, while bypassing a storage unit, by a first port in which the received fetch response data can be set. The fetch response data retrieved from the main storage unit, if unable to be set in the first port, is set in a second port through the storage unit. A transmission control unit performs priority control operation to send out, in accordance with a predetermined priority, the fetch response data set in the first port or the second port to the processor. As a result, the latency is shortened from the time when the fetch response data arrives to the time when the fetch response data is sent out toward the processor in response to a fetch request from the processor.

Abstract: Method and system are provided for managing inactive snapshot blocks. Information regarding inactive blocks is collected and placed in a queue. After the queue reaches a threshold number of inactive blocks, the inactive blocks are compressed and stored as a compressed segment. The compressed segment may include inactive blocks for different snapshot data structures. A compression map structure stores information regarding a plurality of compressed segments, including identifiers identifying different snapshot files which may point to one or more inactive blocks. For each compressed segment, a compression information map identifies the location of each inactive block within the compressed segment and the compression state for each inactive block.

Abstract: A memory management sub-system includes code executable by a processor fir performing selecting a plurality of contexts, and selecting a sample of the separately allocable portions of an address space for each of the contexts. For each of the selected allocable portions, a corresponding portion of the host memory to which the selected allocable portion is mapped is determined, and a count corresponding to a number of separately allocable portions of any context that are commonly mapped to the corresponding portion of the host memory. For each context, a metric is computed that is a function of the counts for that context. Host memory is allocated among the contexts at least in part based on their respective metrics.

Abstract: A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load request is loading a page table entry. The prefetch unit is configured to receive from the load unit a physical address of a first cache line that includes the page table entry specified by the load request. The prefetch unit is further configured to responsively generate a request to prefetch into the cache memory a second cache line. The second cache line is the next physically sequential cache line to the first cache line. In an alternate embodiment, the second cache line is the previous physically sequential cache line to the first cache line rather than the next physically sequential cache line to the first cache line.

Abstract: A remote copy system includes: a host computer; a first storage system connected to the host computer; and a second storage apparatus connected to the first storage system. At least one of the first storage system and the second storage system holds, in a storage part thereof, path information used for performing a remote copy of data therebetween. The host computer references the path information in the storage part; determines whether or not a path required for conducting an operation instructed by a user exists, based on at least one of a type of the remote copy and a direction of the path; and, if the required path does not exist, displays, on a display part, that the necessary path does not exist and why the necessary path does not exist.

Abstract: Systems, methods and computer readable media for cache management. Cache management can operate to organize pages into files and score the respective files stored in a cache memory. The organized pages can be stored to an optical storage media based upon the organization of the files and based upon the score associated with the files.

Abstract: A totaling device includes a first specification unit comprising a first storage unit for storing first dividing information and first interpolation value information, a second storage unit for storing second dividing information and second interpolation value dividing information and a third storage unit for storing information of a totaling information storage unit for storing totaling information; a second specification unit for specifying the third storage unit related to the second dividing information which coincides with second total dividing information or the third storage unit related to the second interpolation value dividing information which coincides with the second total dividing information; and a totaling unit for specifying a totaling information storage unit and storing the totaling information of the totaling target information in the totaling information storage unit.