Abstract: There is a journal area and one or more logical volumes comprising a first logical volume. The journal area is a storage area in which is stored a journal data element, which is a data element that is stored in any storage area of a plurality of storage areas configuring a logical volume, or a data element that is written to the storage area. A controller has a size receiver that receives a write unit size, which is the size of a write data element received from a computer, and a size setting unit that sets the received write unit size in a memory for one or more logical volumes. The size of a journal data element stored in a journal area based on the set write unit size is the write unit size.

Abstract: This storage control apparatus 100 is able sufficiently to manifest the merits of economization of electrical power. The storage control apparatus 100 includes one or more additional storage units 150 which are adapted for the supply of power to them to be turned ON and OFF individually. Each of these additional storage units 150 includes a plurality of storage devices 154 (for example, a plurality of HDDs). When a user actuates a management device 106, and causes one or more RAID groups and a spare HDD for each of these RAID groups to be set within the storage control apparatus 100, an MPU 140 of the storage control apparatus 100 controls the management device 106 to make the user set each RAID group and the spare HDD for it within the same additional storage unit 150.

Abstract: A storage system provides virtual ports, and is able to transfer the virtual ports among physical ports located on multiple storage control units making up the storage system. The storage system is able to manage logical volumes and/or virtual volumes and virtual ports as a group when considering whether to move logical/virtual volumes and/or virtual ports to another storage control unit in the storage system. When the storage system is instructed to transfer volumes, virtual ports, or a group of volumes and virtual ports among the storage control units, the storage system determines whether an inter-unit network will be required to be used following the transfer. When the storage system determines that the inter-unit network will be required if the transfer takes place, the storage system determines and presents an alternate storage control unit for the transfer to avoid use of the inter-unit network, thereby avoiding degraded performance.

Abstract: The present invention is related with the management of memory in environments of limited resources, such as those found for example in a smart card. In a more particular manner, the invention relates to a method of managing the data storage resources of volatile memory, the object of which is to reduce the size of volatile memory necessary to implement the stack of the system, and thereby to reserve more volatile memory available for other needs or procedures of the system or of other applications When the stack grows and comes close to its established limit, the system carries out a transfer of a stack block located in the volatile memory to an area of non-volatile memory, hence this transfer allows a compression of the stack increasing its size in a virtual manner.

Abstract: In one embodiment, a processor implements a store hit load predictor. The store hit load predictor is configured to monitor fetched ops in the processor, and is configured to detect stores that may have previously caused store hit load events. The store hit load predictor is configured to predict that the store will cause a store hit load event again, and is further configured to monitor subsequent fetched ops for the load. The store hit load predictor may locate the load using, e.g., an offset from the store to the load in the code sequence. In response to locating the load, the store hit load predictor may create a dependency of the load on the store, preventing the load from executing out of order with respect to the store. A store hit load event may be avoided in this fashion, at least in some cases.

Abstract: A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.

Abstract: A device includes a memory that includes a number of banks. The device receives requests for accessing the memory, determines the banks to which the requests are intended, determines one or more of the banks that are available, selects one or more of the requests to send to the memory based on the one or more of the banks that are available and have a request to be serviced, and sends the selected one or more requests to the memory.

Abstract: A method of utilizing storage in a storage system comprises prioritizing a plurality of storage areas in the storage system for data recovery with different priorities; and performing data recovery of the storage system at an occurrence of a failure involving one or more of the storage areas in the storage system based on the priorities. Data recovery for one storage area having a higher priority is to occur before data recovery for another storage area having a lower priority in the storage system. In various embodiments, the prioritization is achieved by monitoring the access characteristics, or the priority is specified by the host or management computer based on the usage and/or importance of data stored in the storage system, or the priority is determined by the storage system based on the area assignment/release (i.e., usage) of thin provisioned volumes.

Abstract: A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, and an instruction sequencing unit that fetches instructions for execution by the execution unit. The processor further includes an operand data structure and an address generation accelerator. The operand data structure specifies a first relationship between addresses of sequential accesses within a first address region and a second relationship between addresses of sequential accesses within a second address region. The address generation accelerator computes a first address of a first memory access in the first address region by reference to the first relationship and a second address of a second memory access in the second address region by reference to the second relationship.

Abstract: When an update instruction for updating task data stored in a memory is transmitted through a transaction process performed by an application server, an active node apparatus generates, based on the update instruction, an update log indicating update contents of the task data stored in the memory, and then distributes, in a multicast manner, the generated update log to other standby node apparatuses each with a memory. With this, mirroring among the plurality of memories is controlled.

Abstract: A data storage virtualization subsystem (SVS) for providing storage to a host entity is disclosed. The SVS comprises a storage virtualization controller for connecting to the host entity, at least one physical storage device (PSD) pool, and at least one PSD is designated to be a pool spare PSD to the at least one PSD pool. The at least one PSD pool comprises at least one PSD to store user data or associated redundant information and is given a pool ID for identifying the PSD pool.

Abstract: A method of selecting a target volume in a storage system is provided. The method comprises defining one or more parameters for a plurality of storage volumes in the storage system according to user preference; dynamically collecting information related to the parameters while the storage volumes are used; receiving a request to backup a first source volume in the storage system; and selecting or creating the target volume based on the collected information.

Abstract: When performing asynchronous remote copying, whether or not a disaster has occurred at a main site is judged at a remote site; and if the disaster has occurred, recovery processing is immediately started at the remote site. When asynchronous remote copying is performed between a controller and a controller, the controller transfers remote copy target data in a storage apparatus and command information via a remote copy channel to the controller; and after receiving the remote copy target data, the controller stores the remote copy target data in a storage apparatus; and if the controller fails to receive the command information within a set time period, the controller judges that a disaster has occurred, and then outputs the judgment result to a backup center server; and the backup center server executes recovery processing based on data in the storage apparatus when the disaster has occurred.

Abstract: A disk array controller apparatus (10) is disclosed having at least two logical ports (Logical Port #0-Logical Port #3) for interfacing with a host (12) and having one or more physical ports (Physical Port #0-Physical Port #4), each physical port arranged for attaching at least one disk drive to the controller, and the controller including a switch (26), the switch providing dynamically configurable data paths (30) between the logical data ports and physical data ports, responsive to the contents of a Mapping Register (24). The Mapping Register defines a desired disk drive array by specifying an association of each logical port to one of the physical ports. The mapping register can be organized as a logical mapping register, comprising a field for each logical port of the controller, and includes provision for designating a redundant array for RAID operations.

Abstract: Among others, techniques and apparatus are described for de-interleaving. A data processing apparatus includes a buffer to store interleaved data; an interleaving index producing unit to produce an interleaving index of the interleaved data; and an output control unit to output the data stored in the buffer using the interleaving index.

Abstract: A method (and system) of storing data in a value-based storage system, includes optimizing a value of data stored in the value-based storage system.

Abstract: A method and system for performing logical to physical address translations in a memory is disclosed, wherein the memory includes a translation cache containing a subset of a plurality of entries mapping logical block addresses to physical locations of the memory. Aspects of the exemplary embodiment include receiving from a processor a read/write request for a logical block and context information regarding the logical block, the context information including at least one of a relationship of the logical block to other logical blocks and a description of future activity associated with the logical block; and pre-fetching a first entry into the translation cache based on the context information so that the first entry required to satisfy a future request is available in the translation cache when the future request is received.

Abstract: Methods and apparatus are provided for a solid state non-volatile storage sub-system of a computer. The storage sub-system includes a write-once storage sub-system memory device and a write-many storage sub-system memory device. The write-once storage sub-system memory device includes a recoverable system configuration. Numerous other aspects are provided.

Abstract: A spiral cache memory provides low access latency for frequently-accessed values by self-organizing to always move a requested value to a front-most storage tile of the spiral. If the spiral cache needs to eject a value to make space for a value moved to the front-most tile, space is made by ejecting a value from the cache to a backing store. A buffer along with flow control logic is used to prevent overflow of writes of ejected values to the generally slow backing store. The tiles in the spiral cache may be single storage locations or be organized as some form of cache memory such as direct-mapped or set-associative caches. Power consumption of the spiral cache can be reduced by dividing the cache into an active and inactive partition, which can be adjusted on a per-tile basis. Tile-generated or global power-down decisions can set the size of the partitions.

Abstract: A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism.