Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: A system, method and computer-usable medium are disclosed for recovering data from a memory storage device. The operating system (OS) of an IPS comprising a source memory storage device, further comprising stored data, is monitored to detect a defective operating state. If a defective operating state of the OS is detected, then operation of the IPS is terminated, followed by the initiation of IPS boot operations to recover data from the source memory storage device. The OS is bypassed, and initial boot operations are performed from a management controller or from the BIOS of the IPS. Additional boot operations are performed, and once the IPS has been brought to an operative state, a data recovery module is used to transfer data from the source memory storage device to a target storage device.

Abstract: A new “held” (“H”) cache-coherency state is introduced for directory-based multiprocessor systems. Using the held state enables embodiments of the present invention to track sharers that have a shared copy of a cache line after a directory runs out of space for holding information that identifies processors that have received shared copies of the cache line (e.g., pointers to sharers of the cache line). In these embodiments, when a directory entry is full, the system provides subsequent shared copies of the cache line to sharers in the held state and tracks the identity of the held-copy owners in a data field in the entry for the cache line in a home node.

Abstract: A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory.

Abstract: A detachable storage device can comprise a memory, circuitry, and a user interface. The memory may comprise a storage partition. The circuitry may be configured to authorize access to the storage partition to a digital device when the detachable storage device is coupled to the digital device based, at least in part, on a user code. The user interface may be configured to receive the user code while the detachable storage device is within a detached state and provide the user code to the circuitry to allow access to the storage partition.

Abstract: A modular data and storage management system. The system includes a time variance interface that provides for storage into a storage media of data that is received over time. The time variance interface of the modular data and storage management system provides for retrieval, from the storage media, of an indication of the data corresponding to a user specified date. The retrieved indication of the data provides a user with an option to access specific information relative to the data, such as content of files that are included in the data.

Abstract: In a particular embodiment, a cache is disclosed that includes a tag state array that includes a tag area addressable by a set index. The tag state array also includes a state area addressable by a state address, where the set index and the state address include at least one common bit.

Abstract: A computer system including a first storage system connected to a first host computer, a second storage system connected to a second host computer and a third storage system connected to the first and second storage systems. The second storage system sets transfer setting before an occurrence of a failure, the transfer setting being provided with a dedicated storage area to be used for transferring data to the third storage system by asynchronous copy in response to a failure at the first host computer. Before the start of data transfer between the second storage system and third storage system to be executed after an occurrence of the failure, the second storage system checks the dedicated storage area, data transfer line and transfer setting information, and if an abnormal state is detected, this abnormal state is reported to the host computer as information attached to the transfer setting.

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect.

Abstract: Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.

Abstract: A storage system comprises a plurality of control modules having a plurality of cache memories respectively. One or more dirty data elements out of a plurality of dirty data elements stored in a first cache memory in a first control module are copied to a second cache memory in a second control module. The one or more dirty data elements stored in the second cache memory are backed up to a non-volatile storage resource. The dirty data elements backed up from the first cache memory to the non-volatile storage resource are dirty data elements other than the one or more dirty data elements of which copying has completed, out of the plurality of dirty data elements.

Abstract: A method is provided method for allocating storage space. The method includes obtaining performance parameters for a storage pool, wherein the performance parameters comprise a size of the storage pool and a type of the storage pool. Proposed back end logical units (BELUs) to match the performance parameters are determined. Current disk groups for the proposed BELUs are identified, and if none exists, a plurality of storage arrays is analyzed to locate free disks that can be formed into a proposed disk group to support the creation of the proposed BELUs. A proposal is created showing the changes that would be made to a storage system to create the storage pool.

Abstract: A system for conveying critical and non-critical words of multiple cache lines includes a first node interface of a first processing node receiving, from a first processor, a first request identifying a critical word of a first cache line and a second request identifying a critical word of a second cache line. The first node interface conveys requests corresponding to the first and second requests to a second node interface of a second processing node. The second node interface receives the corresponding requests and conveys the critical words of the first and second cache lines to the first processing node before conveying non-critical words of the first and second cache lines.

Abstract: In order to control an access request to the cache shared between a plurality of threads, a storage unit for storing a flag provided in association with each of the threads is included. If the threads enter the execution of an atomic instruction, a defined value is written to the flags stored in the storage unit. Furthermore, if the atomic instruction is completed, a defined value different from the above defined value is written, thereby displaying whether or not the threads are executing the atomic instruction. If an access request is issued from a certain thread, it is judged whether or not a thread different from the certain thread is executing the atomic instruction by referencing the flag values in the storage unit. If it is judged that another thread is executing the atomic instruction, the access request is kept standby. This makes it possible to realize the exclusive control processing necessary for processing the atomic instruction according to simple configuration.

Abstract: A method for addressing a memory having a plurality of flash memory chips organized in erasable blocks, which in turn contain writable sectors, and where an erase counter is associated with each memory block. The overwriting of the sectors occurs by way of alternative memory blocks searched in the same chip for low erase counter values, as long as a threshold value of the erase counter is not exceeded. The copying operations are conducted efficiently using a copy command internal to the memory chip. As soon as the threshold value is exceeded, alternative memory blocks are searched in other memory chips as well.

Abstract: A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a first prefetch stream, indicating a relative priority for scheduling prefetch operations of the first prefetch stream. The PE monitors activity within the data processing system and dynamically updates the priority of the first prefetch stream based on the activity (or lack thereof). Low priority streams may be discarded. The PE also schedules prefetching in a priority-based scheduling sequence that corresponds to the priority currently assigned to the scheduled active streams. When there are no prefetches within a prefetch queue, the PE triggers the active streams to provide prefetches for issuing. The PE determines when to throttle prefetching, based on the current usage level of resources relevant to completing the prefetch.

Abstract: A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein.

Abstract: A system and method for managing files in a flash memory. The flash memory has a first storage area and a second storage area for storing files. Each of the files has a file header and a data block. The method includes writing the file header of each of the files into the first storage area and setting the first storage area as a first mode, writing the data block of each of the files into the second storage area and setting the second area as a second mode. Responding to the data block of one of the files being completely written into the second storage area, a memory address of the data block stored in the second storage area is written to a corresponding file header.

Abstract: The present invention provides for a method, system, and computer program product for managing the storage of data. Data is selectively compressed based on a pre-defined compression policy and metadata is stored for physical storage blocks. A stored compression policy identifies at least one criterion for compression, and physical blocks of data meeting the compression policy are identified. A physical block is selected as a source block for data compression, and one or more physical locations are selected as target locations. Data is read from the source block, compressed, and written to the target locations. Metadata is updated to indicate a mapping between the target locations and the virtual blocks previously mapped to the source block. Extra storage capacity can be freed up until more physical storage is ordered and installed, while more important data, such as recently or frequently accessed data, is retained in an uncompressed and accessible state.

Abstract: A method and apparatus associated with transferring data from a remote device to a recipient device having a first memory space and a second memory space. The method includes issuing a transfer command from the remote device to request transferring a set of data to the second memory space; temporarily storing the set of data in the first memory space pending a transfer to the second memory space; and appending the set of data to other sequential data in the first memory to obtain a transfer data block of a predetermined size for transfer to the second memory space. A corresponding apparatus is provided comprising circuitry configured to buffer write commands by characterizing each write command as being either a sequential write or a random write, and responsively appending data associated with sequential write commands in order to obtain a transfer block of a predetermined size.