Abstract: In one embodiment, a storage buffer includes a plurality of storage locations configured to store a plurality of incoming instructions. The storage buffer also includes a shift FIFO that is coupled to the plurality of storage locations. The shift FIFO includes an entry configured to store an instruction that is next in a program order. In response to receiving a shift signal, control functionality that is coupled to the plurality of storage locations and to the shift FIFO may cause the instruction that is next in the program order to be moved from a given location of the plurality of storage locations to the entry of the shift FIFO.

Abstract: Proposed are a remote copy system and a remote copy control method capable of performing the operation of remote copy according to the user's usage status. Resource information representing a resource usage status is collected from a first storage apparatus installed at a primary site and a second storage apparatus installed respectively at one or more secondary sites, a transfer mode of differential data between snapshots to be transferred from the first storage apparatus to the second storage apparatus based on the collected resource information, and the first and second storage apparatuses are controlled so as to transfer the differential data from the first storage apparatus to the second storage apparatus based on the decided transfer mode.

Abstract: A method for protecting data, adapted for a computer system, is provided. The computer system includes a storage device. The method includes: when the computer system executes a power-off procedure, inspecting whether a preset external storage device is connected to the computer system; if it is determined that the preset external storage device is connected to the computer system, when the computer system executes the power-off procedure, backing up data of a predetermined segment of the storage device to the preset external storage device, and generating a back-up data, and then writing a specific data template to the predetermined segment for covering original data of the predetermined segment.

Abstract: In one embodiment, a cache comprises a tag memory and a comparator. The tag memory is configured to store tags of cache blocks stored in the cache, and is configured to output at least one tag responsive to an index corresponding to an input address. The comparator is coupled to receive the tag and a tag portion of the input address, and is configured to compare the tag to the tag portion to generate a hit/miss indication. The comparator comprises dynamic circuitry, and is coupled to receive a control signal which, when asserted, is defined to force a first result on the hit/miss indication independent of whether or not the tag portion matches the tag. The comparator also comprises circuitry coupled to receive the control signal and configured to inhibit a state change on an output of the dynamic circuitry during an evaluate phase of the dynamic circuitry to produce the first result responsive to an assertion of the control signal.

Abstract: A portable housing capable of being carried by a certain person includes a circuit. The circuit includes a memory for storing private data concerning that certain person, a circuit operable to effectuate storage of the private data in the memory in a secure manner, and a processing unit operable to control access to the memory for purposes of reading private data concerning the certain person from the memory and storing private data concerning the certain person to the memory. The conditions under which access to the memory for read and write operations with respect to the private data is permitted are governed by parameters that are specified by the certain person to whom the stored private data concerns. A biometric sensor may also be included to capture identification information useful in implementing the operations for controlling access to the memory.

Abstract: A method and apparatus is described herein for providing an optimized file system architecture. A file system is demarcated by configuration headers at the top and bottom of a volume. File headers are stored in the volume for each file, and the file headers included references to a table sector or sectors associated with the file. The table sector(s) are to store entries associated with sectors storing the file. Each entry, which corresponds to a sector of the sectors storing the file, is to store a reference to the corresponding sector and compression information associated with the sector. Based on the compression information, files may be compressed at a sector granularity and decompressed before providing the data in response to read requests.

Abstract: Systems and methods may be provided for lookahead instruction fetching for processors. The systems and methods may include an L1 instruction cache, where the L1 instruction cache may include a plurality of lines of data, where each line of data may include one or more instructions. The systems and methods may also include a tagless hit instruction cache, where the tagless hit instruction cache may store a subset of the lines of data in the L1 instruction cache, where instructions in the lines of data stored in the tagless hit instruction cache may be stored with metadata indicative of whether a next instruction is guaranteed to reside in the tagless hit instruction cache, where an instruction fetcher may be arranged to have direct access to the L1 instruction cache and the tagless hit instruction cache, and where the tagless hit instruction cache may be arranged to have direct access to the L1 instruction cache.

Abstract: A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).

Abstract: A storage apparatus has a channel board 11; a drive board 13; a cache memory 14; a plurality of processor boards 12 that transfer data; and a shared memory 15. The channel board 11 stores a frame transfer table 521 containing information indicative of correspondence between a LDEV 172 and each of the processor boards 12, set in accordance with a right of ownership that is a right of access to the LDEV 172. The processor boards 12 store LDEV control information 524 in a local memory 123, which is referred to by the processor board at the time of access. The channel board 11 transfers a data frame that forms the received data I/O request, to one of the processor boards 12 corresponding to the LDEV 172 specified from the information contained in the frame by using the frame transfer table 521.

Abstract: Efficiently utilizing the bandwidth of the host interface unit even after restoration. A controller manages a storage area of a disk as multiple logical units (LUs), as well as measures the bandwidth used by each host interface unit as load information, stores the load information at the time of the backup, and at the time of the restoration, restores the backup data in logical units in the restoration destination and, with reference to the load information, distributes the paths connecting the logical units in the access source and the logical units in the restoration destination to the host interface units.

Abstract: A system and method for dynamic redistribution of parity groups is described. The system and method for dynamic redistribution of parity groups operates on a computer storage system that includes a plurality of disk drives for storing parity groups. Each parity group includes storage blocks. The storage blocks include one or more data blocks and a parity block that is associated with the data blocks. Each of the storage blocks is stored on a separate disk drive such that no two storage blocks from a given parity set reside on the same disk drive. The computer system further includes a redistribution module to dynamically redistribute parity groups by combining some parity groups to improve storage efficiency.

Abstract: Data are write commanded from a host into a NAND flash memory. The data are saved once in a cache memory before being written into the NAND flash memory. The cache memory includes a physical segment whose size is the product of one page sector size of the NAND flash memory and the m-th power of 2 (m is 0 or a positive integer). A CPU records and manages the data writing status for each physical segment in a sector unit.

Abstract: Methods and systems to selectively map higher-usage addresses to higher-endurance memory cells of a flash memory, and lower-usage addresses to lower-endurance memory cells of the flash memory. Address usage may be determined with respect to the most recent write operation corresponding to an address and/or with respect to a frequency of write operations corresponding to the address. Higher-endurance memory cells may include single level cells (SLCs). Lower-endurance memory cells may include multi-level cells (MLCs). Improved endurance may be obtained with a relatively small percentage of higher-endurance memory cells, at a relatively low cost.

Abstract: An operation method of file system includes retrieving the first header of the first file, adding the auxiliary data to the first header to generate the second header, writing the dummy data into the second header to adjust the data length of the second header, thereby serving as the third header, and modifying the link relation of clusters recorded in the file allocation table such that the third header and the second data segment are linked together, thereby generating the second file.

Abstract: An area detection unit detects a main rectangular area to which an access start address indicated by one-dimensional access information is included among main rectangular areas corresponding to two-dimensional access information. An address conversion unit divides the detected main rectangular area into sub rectangular areas, detects a sub rectangular area to which the access start address indicated by the one-dimensional access information is included, and converts the one-dimensional access information into first two-dimensional access information based on a relative position of the sub rectangular area being detected. A memory controller receives the first and second two-dimensional access information, and converts the two-dimensional access information into an access address. Accordingly, a modification of a memory controller accessing a semiconductor memory by receiving the two-dimensional access information becomes unnecessary.

Abstract: A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.

Abstract: A method, computer program product, and computing system for obtaining N data segments for storage within N data planes included within a flash-memory storage device. Each of the N data planes includes a plurality of data blocks. A superblock is defined, wherein the superblock includes a data block from each of the N data planes included within the flash-memory storage device. Data is; and simultaneously writing data to each data block included within the superblock.

Abstract: A flash memory accessing apparatus is disclosed. The flash memory accessing apparatus includes a memory controller, a first open NAND flash interface (ONFI) and an expanding flash memory module. The first ONFI is used for connecting a main flash memory module. The memory controller obtains a detecting result by, detecting whether the main flash memory module and the expanding flash memory module are single side or double side. The memory controller further configures an accessing method of the main flash memory module and the expanding flash memory module according to the detecting result.

Abstract: The present application includes methods and system for managing a storage device. In one implementation, a storage allocator that is present in a host or a storage device receives a request to store a file in a storage area of the storage device. The storage allocator marks the file as discardable in a file system structure associated with the storage device and updates a primary file allocation table (“FAT”) to associate a cluster chain that is allocated to the file with the file. The storage allocator additionally updates a discardable FAT or a database to reflect a physical location of the file, or may generate one or more location files that store the physical location of the file. The storage allocator then manages the storage area device based on the FAT and a discardable FAT, database, or one more location files indicating the physical location of the file.

Abstract: Disclosed is a method and apparatus embodying a flash translation layer (FTL) in a storage device including a flash memory. The FTL may classify a block into a sequential group and a fusion group based on a locality of a write request. The FTL may store data in blocks of the fusion group by using a page mapping scheme, and sequentially store data by using a block mapping scheme. The FTL may improve efficiency of garbage collection operation that is performed by using limited redundant blocks and also may increase efficiency of a non-sequential reference operation.