Abstract: An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in a plurality of execution environments (EE) selectively wherein a said execution environment (EE) is activated or suspended, a first configuration register (SCR) coupled to the processing circuit (2610) for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment (EE) is activated (EE_Active); and a second configuration register (SSM_FIQ_EE_y) for associating an identification of that execution environment (EE) with the same interrupt request, the processing circuit (2610) coupled (5910) to the second configuration register (SSM_FIQ_EE_y) to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment (EE) is suspended (5920).

Abstract: Improved techniques for communicating between a portable electronic device and an accessory (or auxiliary) device are disclosed. The accessory device can augment or supplement the functionality or capabilities of the portable electronic device. For example, in one embodiment, the accessory device can provide wireless communication capabilities to the portable electronic device. In one embodiment, the portable electronic device pertains to a portable media player and thus provide media data for storage, playback or transmission. In one embodiment, the accessory device is attachable to the portable electronic device.

Abstract: A method of operating a resource lock for controlling access to a resource by a plurality of resource requesters, the resource lock operating in a contention efficient (heavyweight) operating mode, and the method being responsive to a request from a resource requester to acquire the resource lock, the method comprising the steps of: incrementing a count of a total number of acquisitions of the resource lock in the contention efficient operating mode; in response to a determination that access to the resource is not contended by more than one resource requester, performing the steps of: a) incrementing a count of a number of uncontended acquisitions of the resource lock in the contention efficient operating mode; b) calculating a contention rate as the number of uncontended acquisitions in the contention efficient operating mode divided by the total number of acquisitions in the contention efficient operating mode; and c) in response to a determination that the contention rate meets a threshold contention rate

Abstract: There is provided a first dock for a portable hard disk, where the first dock is connectable to a host device. There is also provided a corresponding method for accessing content on the host device during use of the dock. It is advantageous that the host device is able to access content from portable hard disks that are docked with the first dock and a second dock.

Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

Abstract: A data communication system includes one or more data processing units and includes a central control unit. The decentralized data processing units are connected to the central control unit by data connection. The central control unit includes a synchronisation unit for outputting via the data connection an synchronisation signal to the data processing unit. The data processing unit includes a data generator for generating data and transmitting, after the synchronisation signal, data to the central control unit.

Abstract: A method is disclosed in which data is exchanged via a bus coupler (500) between a network (410) designed for transmitting Ethernet telegrams and a lower-level bus system (420), wherein the bus coupler (500) is connected via a first interface (520) to the network (410) and via a second interface (530) to the lower-level bus system (420), and wherein process data is read in and/or output through at least one bus node (610, 620, 630) of the lower-level bus system (420). Furthermore, a bus coupler (500), a bus node (610, 620, 630), and a control system (10) that are designed for execution of the method are disclosed.

Abstract: A communication infrastructure for a data processing apparatus, and a method of operation of such a communication infrastructure are provided. The communication infrastructure provides first and second switching circuits interconnected via a bidirectional link. Both of the switching circuits employ a multi-channel communication protocol, such that for each transaction a communication path is established from an initiating master interface to a target slave interface, with that communication path comprising m channels. The m channels comprise one or more forward channels from the initiating master interface to the target slave interface and one or more reverse channels from the target slave interface to the initiating master interface, and handshaking signals are associated with each of the m channels.

Abstract: A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses.

Abstract: Methods and apparatus, including computer program products, implementing techniques for forming an Advanced Switching (AS) packet by applying AS path binding information to a packet received over a Peripheral Component Interconnect-Express (PCIe) fabric according to a downstream port identifier associated with the packet, and sending the AS packet to an AS fabric. Methods and apparatus, including computer program products, implementing techniques for processing an AS packet received over an AS fabric by comparing an AS payload of the AS packet with one or more memory spaces associated with port identifiers, determining whether the AS payload comprises a base packet to be transmitted to the PCIe fabric based on the comparison, and if so, removing an AS header from the AS packet to reveal the base packet.

Abstract: A system and method for statistics recording of power devices is disclosed. A power circuit includes a power device to provide a specified electrical power to a load and a host controller coupled to the power device. The host controller is configured to provide issue instructions to and retrieve status information from the power device. A communications and control interface (CCI) is coupled between the power device and the host controller. The CCI is configured to operate as a communications interface between the power device and the host controller and to retrieve and store status information from the power device. The CCI may be capable of performing statistical analysis on the status information to help reduce the amount of information exchanged between the host controller and the power device, thereby reducing bandwidth requirements.

Abstract: A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a transmit buffer is preferably provided for every other device on the bus with which it will communicate. One or more logic circuits, for example, a scheduler, is provided to coordinate exchange transactions between pairs of devices. Time delays are preferably provided between exchange transactions of different device pairs so as to prevent interference. Coherency checking is preferably implemented to avoid discrepancies introduced by information being held in a buffer pending an exchange transaction.

Abstract: A dual host system and method with back to back non-transparent bridges and a proxy packet generating mechanism. The proxy packet generating mechanism enables the hosts to send interrupt generating packets to each other.

Abstract: A method of adjusting wafer process sequence includes steps of collecting production parameters for a plurality of lots; selecting a plurality of key parameters from the production parameters, wherein the key parameters at least includes a processing sequence; defining a formula to obtain an epsilon value; categorizing the lots into groups according to the epsilon value and the minimum point number by using density-based spatial clustering of application with noise (DBSCAN); and adjusting the processing sequences of the lots in the groups. Thereby, the lots with the same process recipe can be continuously or simultaneously sent into a machine, thereby reducing replacement of process recipes or shortening machine idle time.

Abstract: A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Abstract: A multiprocessor control unit acquires first non processing time information on a first non processing time represented for each processor, wherein the first non processing time represents a time in which a first block is not executed in a first barrier establishment time from barrier synchronization start until barrier synchronization establishment of the first program block, and acquires second non processing time information on a second non processing time represented for each processor, wherein the second non processing time represents a time in which a second block is not processed in a second barrier establishment time from barrier synchronization start until barrier synchronization establishment of the second program block. The multiprocessor control unit controls a power supply for the processors while the first and second program blocks are consecutively executed in parallel, using the first and second non processing time information acquired.

Abstract: An arbiter, a system, and a method for generating a pseudo-grant signal in response to a request and receiving target information in response to the pseudo-grant signal. The pseudo-grant signal reduces or eliminates waiting time.

Abstract: In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.

Abstract: A method for generating a device description for a measuring apparatus in a target field bus protocol is described. The method comprises the reception of a first device description of the apparatus. The first device description of the apparatus comprises at least one variable. The at least one variable is related to a storage cell of the apparatus. The target field bus protocol is selected from a plurality of field bus protocols, and at least one block is formed from the at least one variable. The at least one block has a maximum block size that corresponds to the smallest maximum block size of at least two field bus protocols of the plurality of field bus protocols. The maximum block size can be transmitted via a field bus with a single request when the respective field bus protocol is used. Subsequently, the at least one block is provided as device description for the apparatus in the target field bus protocol.

Abstract: A semiconductor device includes an interface controller for communication with a memory device over a communication link. The link includes a plurality of data lines for transmitting data. A plurality of bus width values are defined, each being a selectable number of data lines over which data are to be transmitted. The number of data lines is in the range between one and the number of the plurality of data lines. The interface controller is dynamically configurable to any of the defined bus width values, which becomes the current bus width. The transmission over each data line may be selectably in either direction. The transmission over all data lines corresponding to the current bus width may collectively carry, in at least one direction, command codes, memory addresses, and data in an intermixed manner.